Abstract: A system, method, and computer program product for implementing microservice deployment is provided. The method includes receiving definitions associated with microservices related to implementing hardware and software solutions with respect to hardware and software systems. In response, a definition file and associated code comprising the definitions and associated dependencies associated with the microservices are generated. The microservices are deployed to a container orchestration system cluster on a cloud structure and a service mesh and machine learning module are installed within the container orchestration system cluster. Proxies comprising a proxy for each pair of dependencies are generated and network traffic passing through each proxy is monitored. A malfunction of a hardware or software system is detected and an associated network route passing through an associated proxy is disabled.

Abstract: A multi-port memory is provided that supports collision between a read port and a write port to the same multi-port bitcell. A sense amplifier reads a data bit from a multi-port bitcell when a write port to the multi-port bitcell is addressed during a system clock signal. Should a read port to the multi-port bitcell be addressed during the same system clock signal, a multiplexer selects for an output bit from the sense amplifier.

Abstract: Embodiments of the present invention provide a computer system a computer program product, and a method that comprises converting the retrieved data to a uniform syntax for data assessment; performing a query on a plurality of external data sources for additional information associated with the converted data; analyzing a plurality of indicative markers associated with the retrieved data and the additional information; generating a plurality of machine learning models associated with the converted data based on the analysis of each indicative markers within the plurality of indicative markers; dynamically selecting at least one generated machine learning model within the plurality of generated machine learning models associated with the retrieved data based on an analysis of the plurality of indicative markers associated with the retrieved data and the additional information; and automatically verifying an accuracy value associated with the at least one selected generated machine learning model.

Abstract: Computer-implemented methods, computer program products, and computer systems for testing a voice assistant device may include one or more processors configured for receiving test data from a database, wherein the test data may include a first set of coding parameters and a first user utterance having an expected device response. Further, the one or more processors may be configured for generating a first modified user utterance by applying the first set of coding parameters to the first user utterance, wherein the first modified user utterance is acoustically different than the first user utterance. The one or more processors may be configured for audibly presenting the first modified user utterance to a voice assistant device, receiving a first device response from the voice assistant device, and determining whether the first voice assistant response is substantially similar to the expected device response.

Abstract: Certain aspects of the present disclosure are directed to a memory circuit. The memory circuit generally includes a memory cell coupled between a bit-line and a complementary bit-line. The memory circuit also includes a first n-type metal-oxide-semiconductor (NMOS) transistor configured to couple the bit-line to a write drive input during a write cycle of the memory circuit. The memory circuit also includes a second NMOS transistor configured to couple the complementary bit-line to a complementary write drive input during the write cycle, and a multiplexer circuit having a first p-type metal-oxide-semiconductor (PMOS) transistor coupled between a voltage rail and the bit-line or the complementary bit-line, the multiplexer circuit being configured to couple, via the first PMOS transistor, the bit-line or the complementary bit-line to the voltage rail during the write cycle.

Abstract: A memory and method of performing a write operation in a memory are disclosed. In one aspect of the disclosure, the memory includes a memory cell, a pair of bit lines coupled to the memory cell, a multiplexer, and a pull-up circuit coupled to the multiplexer. The multiplexer may be configured to select the pair of bit lines coupled to the memory cell during the write operation. To increase the write performance of the memory cell, the pull-up circuit is configured to select which of the pair of bit lines is a non-zero bit line during the write operation and to clamp the non-zero bit line through the multiplexer to approximately a power rail voltage. Thus, the pull-up circuit may increase the voltage difference between the non-zero bit line and the zero bit line during the write operation and thus decrease the area and power consumed by a boost capacitance.

Abstract: A memory is provided that includes a negative bit line boost circuit for boosting a discharged bit line to a negative voltage during a negative bit line boost period for a write operation to a selected column in the memory. The memory also includes a core voltage control circuit configured to float a core power supply voltage for the selected column during the negative bit line boost period.

Abstract: Methods and apparatuses to adjust wordline voltage level are presented. An apparatus includes multiple memory cells arranged in multiple rows. A wordline is configured to couple to one row of the multiple rows for a read or write operation. A wordline driving circuit is configured to provide a voltage level to the wordline to facilitate the read or write operation. A tracking circuit is configured to emulate a characteristic of one of the multiple memory cells. A pull-down circuit is configured to lower the voltage level of the wordline by an amount, based on the tracking circuit, to access the one row of the multiple rows in the read or write operation. A method includes emulating a characteristic of one of multiple of memory cells and lowering a voltage level of the wordline by an amount to access one row of the multiple rows in the read or write operation.

Abstract: Methods and apparatuses to adjust wordline voltage level are presented. An apparatus includes multiple memory cells arranged in multiple rows. A wordline is configured to couple to one row of the multiple rows for a read or write operation. A wordline driving circuit is configured to provide a voltage level to the wordline to facilitate the read or write operation. A tracking circuit is configured to emulate a characteristic of one of the multiple memory cells. A pull-down circuit is configured to lower the voltage level of the wordline by an amount, based on the tracking circuit, to access the one row of the multiple rows in the read or write operation. A method includes emulating a characteristic of one of multiple of memory cells and lowering a voltage level of the wordline by an amount to access one row of the multiple rows in the read or write operation.

Abstract: A memory and method of performing a write operation in a memory are disclosed. In one aspect of the disclosure, the memory includes a memory cell, a pair of bit lines coupled to the memory cell, a multiplexer, and a pull-up circuit coupled to the multiplexer. The multiplexer may be configured to select the pair of bit lines coupled to the memory cell during the write operation. To increase the write performance of the memory cell, the pull-up circuit is configured to select which of the pair of bit lines is a non-zero bit line during the write operation and to clamp the non-zero bit line through the multiplexer to approximately a power rail voltage. Thus, the pull-up circuit may increase the voltage difference between the non-zero bit line and the zero bit line during the write operation and thus decrease the area and power consumed by a boost capacitance.

Abstract: A pair of write driver inverters are arranged in series to drive a bit line responsive to a data bit input signal. A first boost capacitor provides a negative boost to a first ground node for a first one of the write driver inverters during the write assist period. A second boost capacitor provides a negative boost to a second ground node for a second one of the write driver inverters during the write assist period.

Abstract: A write driver is provided that includes a first write driver inverter that inverts a data signal to drive a gate of a second write driver transistor. The write driver transistor has a terminal coupled to a bit line and another terminal coupled to a boost capacitor. A ground for the first write driver inverter floats during a write assist period to choke off leakage of boost charge from the boost capacitor through the write driver transistor.

Abstract: A memory and apparatus are disclosed. The memory includes a memory core having a plurality of memory cells. The memory also includes a first write assist circuit configured to assist writing to a first group of the plurality of memory cells of the memory core. Additionally, the memory includes a second write assist circuit configured to assist writing to a second group of the plurality of memory cells of the memory core. The apparatus includes at least one processor. The apparatus also includes a memory array. The memory array includes a memory core having a plurality of memory cells. The memory also includes a first write assist circuit configured to assist writing to a first group of the plurality of memory cells of the memory core and a second write assist circuit configured to assist writing to a second group of the plurality of memory cells of the memory core.

Abstract: Various implementations described herein are directed to an integrated circuit for read-write contention. The integrated circuit may include a memory circuit having multiple ports configured to receive data signals corresponding to each port. The integrated circuit may include a contention override circuit providing a contention override signal for each port based on detecting a read-write contention between the ports. The integrated circuit may include a write circuit having multiple passgates for each port including write passgates and contention passgates for each port. The write passgates may be input with data signals from corresponding ports. The contention passgates may be input with data signals from opposing ports based on opposing contention override signals.

Abstract: Various implementations described herein are directed to an integrated circuit for read-write contention. The integrated circuit may include a memory circuit having multiple ports configured to receive data signals corresponding to each port. The integrated circuit may include a contention override circuit providing a contention override signal for each port based on detecting a read-write contention between the ports. The integrated circuit may include a write circuit having multiple passgates for each port including write passgates and contention passgates for each port. The write passgates may be input with data signals from corresponding ports. The contention passgates may be input with data signals from opposing ports based on opposing contention override signals.

Abstract: Waveguide based connector systems for optically coupling a fiber optic cable and an optoelectronic device and a method of fabricating the same are described. In one aspect, a connector system comprises an optical waveguide and an optical turn assembly. The optical waveguide has a first end and a second end. The first end of the optical waveguide is connectable to the fiber optic cable in an orientation aligned with a line-side connection axis. The optical turn assembly has a first optical port that is connected to the second end of the optical waveguide in an orientation aligned with a device-side connection axis, a second optical port that is oriented to communicate optically with the optoelectronic device along a device communication axis substantially intersecting the device-side connection axis, and an optical turn system that is operable to guide light along a path between the first optical port and the second optical port.