Abstract: A write driver is provided that includes a first write driver inverter that inverts a data signal to drive a gate of a second write driver transistor. The write driver transistor has a terminal coupled to a bit line and another terminal coupled to a boost capacitor. A ground for the first write driver inverter floats during a write assist period to choke off leakage of boost charge from the boost capacitor through the write driver transistor.

Abstract: A memory and apparatus are disclosed. The memory includes a memory core having a plurality of memory cells. The memory also includes a first write assist circuit configured to assist writing to a first group of the plurality of memory cells of the memory core. Additionally, the memory includes a second write assist circuit configured to assist writing to a second group of the plurality of memory cells of the memory core. The apparatus includes at least one processor. The apparatus also includes a memory array. The memory array includes a memory core having a plurality of memory cells. The memory also includes a first write assist circuit configured to assist writing to a first group of the plurality of memory cells of the memory core and a second write assist circuit configured to assist writing to a second group of the plurality of memory cells of the memory core.

Abstract: Various implementations described herein are directed to an integrated circuit for read-write contention. The integrated circuit may include a memory circuit having multiple ports configured to receive data signals corresponding to each port. The integrated circuit may include a contention override circuit providing a contention override signal for each port based on detecting a read-write contention between the ports. The integrated circuit may include a write circuit having multiple passgates for each port including write passgates and contention passgates for each port. The write passgates may be input with data signals from corresponding ports. The contention passgates may be input with data signals from opposing ports based on opposing contention override signals.

Abstract: Various implementations described herein are directed to an integrated circuit for read-write contention. The integrated circuit may include a memory circuit having multiple ports configured to receive data signals corresponding to each port. The integrated circuit may include a contention override circuit providing a contention override signal for each port based on detecting a read-write contention between the ports. The integrated circuit may include a write circuit having multiple passgates for each port including write passgates and contention passgates for each port. The write passgates may be input with data signals from corresponding ports. The contention passgates may be input with data signals from opposing ports based on opposing contention override signals.

Abstract: Waveguide based connector systems for optically coupling a fiber optic cable and an optoelectronic device and a method of fabricating the same are described. In one aspect, a connector system comprises an optical waveguide and an optical turn assembly. The optical waveguide has a first end and a second end. The first end of the optical waveguide is connectable to the fiber optic cable in an orientation aligned with a line-side connection axis. The optical turn assembly has a first optical port that is connected to the second end of the optical waveguide in an orientation aligned with a device-side connection axis, a second optical port that is oriented to communicate optically with the optoelectronic device along a device communication axis substantially intersecting the device-side connection axis, and an optical turn system that is operable to guide light along a path between the first optical port and the second optical port.