Patents by Inventor Pradeep Ramachandramurthy Yelehanka
Pradeep Ramachandramurthy Yelehanka has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20080032513Abstract: An integrated circuit system including loading a wafer into a processing chamber and pre-purging the processing chamber with a first ammonia gas. Depositing a first nitride layer over the wafer and purging the processing chamber with a second ammonia gas. Depositing a second nitride layer over the first nitride layer that is misaligned with the first nitride layer. Post-purging the processing chamber with a third ammonia gas and purging the processing chamber with a nitrogen gas.Type: ApplicationFiled: July 5, 2006Publication date: February 7, 2008Applicant: CHARTERED SEMICONDUCTOR MANUFACTURING LTD.Inventors: Sripad Sheshagiri Nagarad, Hwa Weng Koh, Dong Kyun Sohn, Xiaoyu Chen, Louis Lim, Sung Mun Jung, Chiew Wah Yap, Pradeep Ramachandramurthy Yelehanka, Nitin Kamat
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Patent number: 7183590Abstract: An integrated circuit structure includes providing a semiconductor substrate and forming a trench therein. A thyristor is formed around the trench and within the semiconductor substrate. The thyristor has at least four layers with three P-N junctions therebetween. A gate for the thyristor is formed within the trench. An access transistor is formed on the semiconductor substrate. An interconnect is formed between the thyristor and the access transistor.Type: GrantFiled: June 6, 2006Date of Patent: February 27, 2007Assignee: Chartered Semiconductor Manufacturing Ltd.Inventors: Jia Zhen Zheng, Weining Li, Tze Ho Simon Chan, Pradeep Ramachandramurthy Yelehanka
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Patent number: 7148522Abstract: An integrated circuit structure includes a semiconductor substrate and a thyristor formed thereon. The thyristor has at least four layers, with three P-N junctions therebetween. At least two of the layers are formed horizontally and at least two of the layers are formed vertically. A gate is formed adjacent at least one of the vertically formed layers. An access transistor is formed on the semiconductor substrate, and an interconnect is formed between the thyristor and the access transistor.Type: GrantFiled: December 11, 2004Date of Patent: December 12, 2006Assignee: Chartered Semiconductor Manufacturing Ltd.Inventors: Elgin Quek, Pradeep Ramachandramurthy Yelehanka, Jia Zhen Zheng, Tommy Lai, Weining Li
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Patent number: 7119005Abstract: An integrated circuit is provided. A gate dielectric and a gate are provided respectively on and over a semiconductor substrate. A junction is formed adjacent the gate dielectric and a shaped spacer is formed around the gate. A spacer is formed under the shaped spacer and a liner is formed under the spacer. A first dielectric layer is formed over the semiconductor substrate, the shaped spacer, the spacer, the liner, and the gate. A second dielectric layer is formed over the first dielectric layer. A local interconnect opening is formed in the second dielectric layer down to the first dielectric layer. The local interconnect opening in the first dielectric layer is opened to expose the junction in the semiconductor substrate and the first gate. The local interconnect openings in the first and second dielectric layers are filled with a conductive material.Type: GrantFiled: January 27, 2005Date of Patent: October 10, 2006Assignee: Chartered Semiconductor Manufacturing Ltd.Inventors: Pradeep Ramachandramurthy Yelehanka, Tong Qing Chen, Zhi Yong Han, Jia Zhen Zheng, Kelvin Ong, Tian Hao Gu, Syn Kean Cheah
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Patent number: 7081378Abstract: A method for manufacturing an integrated circuit structure includes providing a semiconductor substrate and forming a trench therein. A thyristor is formed around the trench and within the semiconductor substrate. The thyristor has at least four layers with three P-N junctions therebetween. A gate for the thyristor is formed within the trench. An access transistor is formed on the semiconductor substrate. An interconnect is formed between the thyristor and the access transistor.Type: GrantFiled: January 5, 2004Date of Patent: July 25, 2006Assignee: Chartered Semiconductor Manufacturing Ltd.Inventors: Jia Zhen Zheng, Weining Li, Tze Ho Simon Chan, Pradeep Ramachandramurthy Yelehanka
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Patent number: 7067362Abstract: A method for manufacturing an integrated circuit structure includes providing a semiconductor substrate and forming at least one oxide-nitride-oxide dielectric layer above the semiconductor substrate. At least one implantation is formed into at least one area of the semiconductor substrate beneath the oxide-nitride-oxide dielectric layer subsequent to the formation of the oxide-nitride-oxide dielectric layer.Type: GrantFiled: October 17, 2003Date of Patent: June 27, 2006Assignee: Chartered Semiconductor Manufacturing Ltd.Inventors: Tommy Lai, Pradeep Ramachandramurthy Yelehanka, Jia Zhen Zheng, Weining Li
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Patent number: 7015101Abstract: A method for manufacturing an integrated circuit structure includes providing a semiconductor substrate and forming a gate dielectric layer over the semiconductor substrate. The gate dielectric layer is formed in a plurality of thicknesses in a plurality of devices regions over the semiconductor substrate. A second dielectric layer is formed over at least one of the devices regions. A third dielectric layer is formed over at least a portion of the second dielectric layer. Ion traps are then selectively implanted in portions of the second dielectric layer.Type: GrantFiled: October 9, 2003Date of Patent: March 21, 2006Assignee: Chartered Semiconductor Manufacturing Ltd.Inventors: Jia Zhen Zheng, Pradeep Ramachandramurthy Yelehanka, Weining Li
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Publication number: 20050148118Abstract: A method for manufacturing an integrated circuit structure includes providing a semiconductor substrate and forming a trench therein. A thyristor is formed around the trench and within the semiconductor substrate. The thyristor has at least four layers with three P-N junctions therebetween. A gate for the thyristor is formed within the trench. An access transistor is formed on the semiconductor substrate. An interconnect is formed between the thyristor and the access transistor.Type: ApplicationFiled: January 5, 2004Publication date: July 7, 2005Applicant: CHARTERED SEMICONDUCTOR MANUFACTURING LTD.Inventors: Jia Zheng, Weining Li, Tze Chan, Pradeep Ramachandramurthy Yelehanka
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Publication number: 20050098794Abstract: An integrated circuit structure includes a semiconductor substrate and a thyristor formed thereon. The thyristor has at least four layers, with three P-N junctions therebetween. At least two of the layers are formed horizontally and at least two of the layers are formed vertically. A gate is formed adjacent at least one of the vertically formed layers. An access transistor is formed on the semiconductor substrate, and an interconnect is formed between the thyristor and the access transistor.Type: ApplicationFiled: December 11, 2004Publication date: May 12, 2005Applicant: CHARTERED SEMICONDUCTOR MANUFACTURING LTD.Inventors: Elgin Quek, Pradeep Ramachandramurthy Yelehanka, Jia Zheng, Tommy Lai, Weining Li
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Publication number: 20050101102Abstract: A method for manufacturing an integrated circuit structure includes providing a semiconductor substrate and forming two trenches in the semiconductor substrate to define an active region therebetween. An implanted source region is formed in one of the trenches on one side of the active region. An implanted drain region is formed in the other trench on the other side of the active region. Shallow trench isolations are then formed in the trenches. One or more gates are formed over the active region, and contacts to the implanted source region and the implanted drain region are formed.Type: ApplicationFiled: November 6, 2003Publication date: May 12, 2005Applicant: CHARTERED SEMICONDUCTOR MANUFACTURING LTD.Inventors: Tze Ho Chan, Weining Li, Elgin Quek, Jia Zheng, Pradeep Ramachandramurthy Yelehanka, Tommy Lai
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Publication number: 20050085056Abstract: A method for manufacturing an integrated circuit structure includes providing a semiconductor substrate and forming at least one oxide-nitride-oxide dielectric layer above the semiconductor substrate. At least one implantation is formed into at least one area of the semiconductor substrate beneath the oxide-nitride-oxide dielectric layer subsequent to the formation of the oxide-nitride-oxide dielectric layer.Type: ApplicationFiled: October 17, 2003Publication date: April 21, 2005Applicant: CHARTERED SEMICONDUCTOR MANUFACTURING LTD.Inventors: Tommy Lai, Pradeep Ramachandramurthy Yelehanka, Jia Zheng, Weining Li
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Publication number: 20050079674Abstract: A method for manufacturing an integrated circuit structure includes providing a semiconductor substrate and forming a gate dielectric layer over the semiconductor substrate. The gate dielectric layer is formed in a plurality of thicknesses in a plurality of devices regions over the semiconductor substrate. A second dielectric layer is formed over at least one of the devices regions. A third dielectric layer is formed over at least a portion of the second dielectric layer. Ion traps are then selectively implanted in portions of the second dielectric layer.Type: ApplicationFiled: October 9, 2003Publication date: April 14, 2005Applicant: CHARTERED SEMICONDUCTOR MANUFACTURING LTD.Inventors: Zia Zheng, Pradeep Ramachandramurthy Yelehanka, Weining Li
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Publication number: 20050026337Abstract: A method for manufacturing an integrated circuit structure includes providing a semiconductor substrate and forming a thyristor thereon. The thyristor has at least four layers, with three P—N junctions therebetween. At least two of the layers are formed horizontally and at least two of the layers are formed vertically. A gate is formed adjacent at least one of the vertically formed layers. An access transistor is formed on the semiconductor substrate, and an interconnect is formed between the thyristor and the access transistor.Type: ApplicationFiled: July 28, 2003Publication date: February 3, 2005Applicant: CHARTERED SEMICONDUCTOR MANUFACTURING LTD.Inventors: Elgin Quek, Pradeep Ramachandramurthy Yelehanka, Jia Zheng, Tommy Lai, Weining Li
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Patent number: 6849481Abstract: A method for manufacturing an integrated circuit structure includes providing a semiconductor substrate and forming a thyristor thereon. The thyristor has at least four layers, with three P-N junctions therebetween. At least two of the layers are formed horizontally and at least two of the layers are formed vertically. A gate is formed adjacent at least one of the vertically formed layers. An access transistor is formed on the semiconductor substrate, and an interconnect is formed between the thyristor and the access transistor.Type: GrantFiled: July 28, 2003Date of Patent: February 1, 2005Assignee: Chartered Semiconductor Manufacturing Ltd.Inventors: Elgin Quek, Pradeep Ramachandramurthy Yelehanka, Jia Zhen Zheng, Tommy Lai, Weining Li
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Publication number: 20040155269Abstract: An integrated circuit, and manufacturing method therefor, is provided. A gate dielectric and a gate are provided respectively on and over a semiconductor substrate. A junction is formed adjacent the gate dielectric and a shaped spacer is formed around the gate. A spacer is formed under the shaped spacer and a liner is formed under the spacer. A first dielectric layer is formed over the semiconductor substrate, the shaped spacer, the spacer, the liner, and the gate. A second dielectric layer is formed over the first dielectric layer. A local interconnect opening is formed in the second dielectric layer down to the first dielectric layer. The local interconnect opening in the first dielectric layer is opened to expose the junction in the semiconductor substrate and the first gate. The local interconnect openings in the first and second dielectric layers are filled with a conductive material.Type: ApplicationFiled: February 7, 2003Publication date: August 12, 2004Applicant: Chartered Semiconductor Mfg. Ltd.Inventors: Pradeep Ramachandramurthy Yelehanka, Tong Qing Chen, Zhi Yong Han, Jia Zhen Zheng, Kelvin Ong, Tian Hao Gu, Syn Kean Cheah