Patents by Inventor Pradip Kumar Roy

Pradip Kumar Roy has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 7605064
    Abstract: A method of manufacture for semiconductor electronic products and a circuit structure. A semiconductor material has a surface region and dopant is provided to a portion of the surface region. The portion of the surface region provided with the dopant is irradiated with sufficient energy to induce diffusion of the dopant from the portion of the surface region to another region of the semiconductor material. A method for manufacturing an electronic product with a semiconductor material having a surface and two spaced-apart regions along the surface for receiving dopant includes forming a field effect transistor gate structure is along the surface and over a third region of the surface between the two spaced-apart regions. Dopant is provided to the spaced-apart regions which are heated to a temperature at least 50 degrees C. higher than the peak temperature which results in the third region when the spaced-apart regions are heated.
    Type: Grant
    Filed: May 22, 2006
    Date of Patent: October 20, 2009
    Assignee: Agere Systems Inc.
    Inventors: Isik C. Kizilyalli, Joseph Rudolph Radosevich, Pradip Kumar Roy
  • Patent number: 7151059
    Abstract: A reduced feature size MOS transistor and its method of manufacture is disclosed. The present invention reduces short channel effects but does not include an LDD structure In an illustrative embodiment, a MOS transistor has a gate length of 1.25 ?m or less. The exemplary MOS transistor includes a gate oxide that forms a planar and substantially stress free interface with a substrate. As a result of the planarity and substantially stress free nature of the oxide/substrate interface, the incidence of hot carriers, and thereby, deleterious hot carrier effects are reduced. By eliminating the use of the LDD structure, fabrication complexity is reduced and series source-drain resistance is reduced resulting in improved drive current and switching speed.
    Type: Grant
    Filed: January 22, 2004
    Date of Patent: December 19, 2006
    Assignee: Agere Systems Inc.
    Inventors: Samir Chaudhry, Sidhartha Sen, Sundar Srinivasan Chetlur, Richard William Gregor, Pradip Kumar Roy
  • Patent number: 7148153
    Abstract: A process for forming an oxide layer includes forming a first oxide portion over a substrate at a temperature below a threshold temperature. A second oxide portion is formed under the first oxide portion at a temperature above the threshold temperature. The substrate is illustratively oxidizable silicon and the threshold temperature is the viscoelastic temperature of silicon dioxide.
    Type: Grant
    Filed: December 11, 2002
    Date of Patent: December 12, 2006
    Assignee: Agere Systems Inc.
    Inventors: Yuanning Chen, Sundar Srinivasan Chetlur, Pradip Kumar Roy
  • Publication number: 20040150014
    Abstract: A reduced feature size MOS transistor and its method of manufacture is disclosed. The present invention reduces short channel effects but does not include an LDD structure In an illustrative embodiment, a MOS transistor has a gate length of 1.25 &mgr;m or less. The exemplary MOS transistor includes a gate oxide that forms a planar and substantially stress free interface with a substrate. As a result of the planarity and substantially stress free nature of the oxide/substrate interface, the incidence of hot carriers, and thereby, deleterious hot carrier effects are reduced. By eliminating the use of the LDD structure, fabrication complexity is reduced and series source-drain resistance is reduced resulting in improved drive current and switching speed.
    Type: Application
    Filed: January 22, 2004
    Publication date: August 5, 2004
    Inventors: Samir Chaudhry, Sidhartha Sen, Sundar Srinivasan Chetlur, Richard William Gregor, Pradip Kumar Roy
  • Patent number: 6740912
    Abstract: A reduced feature size MOS transistor and its method of manufacture is disclosed. The present invention reduces short channel effects but does not include an LDD structure In an illustrative embodiment, a MOS transistor has a gate length of 1.25 &mgr;m or less. The exemplary MOS transistor includes a gate oxide that forms a planar and substantially stress free interface with a substrate. As a result of the planarity and substantially stress free nature of the oxide/substrate interface, the incidence of hot carriers, and thereby, deleterious hot carrier effects are reduced. By eliminating the use of the LDD structure, fabrication complexity is reduced and series source-drain resistance is reduced resulting in improved drive current and switching speed.
    Type: Grant
    Filed: June 20, 2000
    Date of Patent: May 25, 2004
    Assignee: Agere Systems Inc.
    Inventors: Samir Chaudhry, Sidharta Sen, Sundar Srinivasan Chetlur, Richard William Gregor, Pradip Kumar Roy
  • Patent number: 6720604
    Abstract: The present invention provides a capacitor comprising a conductive plug comprising a top surface and exposed sidewalls, wherein the sidewalls comprise a layer selected from the group consisting of titanium and titanium nitride, and an electrode material layer over the conductive plug sidewalls, wherein the layer of electrode material is not titanium nor titanium nitride.
    Type: Grant
    Filed: February 16, 1999
    Date of Patent: April 13, 2004
    Assignee: Agere Systems Inc.
    Inventors: Larry Bruce Fritzinger, Nace Layadi, Sailesh Mansinh Merchant, Pradip Kumar Roy
  • Patent number: 6670242
    Abstract: A method for making an integrated circuit device includes forming source and drain regions in a semiconductor substrate and defining a channel region therebetween, forming a graded, grown, gate oxide layer adjacent the channel region, forming a nitride layer adjacent the gate oxide layer, and forming a gate electrode layer adjacent the nitride layer. The gate oxide layer may be formed by growing a first oxide portion by upwardly ramping the channel region to a first temperature lower than a glass transition temperature, and exposing the channel region to an oxidizing ambient at the first temperature and for a first time period. A second oxide portion may be grown between the first oxide portion and the channel region by exposing the channel region to an oxidizing ambient at a second temperature higher than the glass transition temperature for a second time period so that the second oxide portion has a thickness in a range of about 2% to about 75% of a total thickness of the gate oxide layer.
    Type: Grant
    Filed: August 30, 2000
    Date of Patent: December 30, 2003
    Assignee: Agere Systems Inc.
    Inventors: David Charles Brady, Yi Ma, Pradip Kumar Roy
  • Patent number: 6659846
    Abstract: An improved polishing pad (22) for use in a chemical mechanical polishing (CMP) operation as part of a semiconductor device fabrication process. The polishing pad is formed of a plurality of particles of abrasive material (24) disposed in a matrix material (26). The abrasive particles may be a stiff inorganic material coated with a coupling agent, and the matrix material may be a polymeric material such as polyurethane. As the polishing pad wears through repeated polishing operations, the newly exposed polishing surface will contain fresh abrasive particles and will exhibit the same polishing properties as the original surface, thereby providing consistent polishing performance throughout the life of the pad without the need for conditioning operations. In one embodiment the distribution of particles of abrasive material per unit volume of matrix material may vary from one portion (23) of the pad to another (25).
    Type: Grant
    Filed: September 17, 2001
    Date of Patent: December 9, 2003
    Assignee: Agere Systems, Inc.
    Inventors: Sudhanshu Misra, Pradip Kumar Roy
  • Patent number: 6616965
    Abstract: Tantalum and niobium aluminum-doped hydrated mixed metal oxide sols may be made by a process comprising combining a first metal compound aluminum alkoxide, with a second metal compound selected from the group consisting of niobium alkoxide and tantalum alkoxide, and mixtures thereof to provide a substantially water-free precursor and combining the precursor with a ketone to provide a hydrated mixed metal oxide sol, wherein the ketone is substantially free of water. The sol may then be processed to obtain thin films, fibers, crystals (both micro- and meso-porous), powders and macroscopic objects and to provide mixed metal oxide that may be used in a variety of components of integrated circuits.
    Type: Grant
    Filed: March 23, 2000
    Date of Patent: September 9, 2003
    Assignee: Agere Systems Inc.
    Inventors: Sudhanshu Misra, Pradip Kumar Roy
  • Publication number: 20030143863
    Abstract: A process for forming an oxide layer includes forming a first oxide portion over a substrate at a temperature below a threshold temperature. A second oxide portion is formed under the first oxide portion at a temperature above the threshold temperature. The substrate is illustratively oxidizable silicon and the threshold temperature is the viscoelastic temperature of silicon dioxide.
    Type: Application
    Filed: February 7, 2003
    Publication date: July 31, 2003
    Applicant: Agere Systems Inc.
    Inventors: Yuanning Chen, Sundar Srinivasan Chetlur, Pradip Kumar Roy
  • Patent number: 6599837
    Abstract: The present invention provides a chemical mechanical planarization (CMP) polishing composition that polishes metal layers at a good removal rate and that provides good planarization of metal layers in a process that can be readily controlled. The CMP polishing composition of the present composition includes a plurality of abrasive particles, a triazole or a triazole derivative, a ferricyanide salt oxidizing agent and water and has a pH of from about 1 to about 6. In addition, the present invention includes a method for removing at least a portion of a metallization layer by polishing a metallization layer using the CMP polishing composition of the invention.
    Type: Grant
    Filed: February 29, 2000
    Date of Patent: July 29, 2003
    Assignee: Agere Systems Guardian Corp.
    Inventors: Sailesh Mansinh Merchant, Sudhanshu Misra, Pradip Kumar Roy
  • Publication number: 20030119337
    Abstract: A process for forming an oxide layer includes forming a first oxide portion over a substrate at a temperature below a threshold temperature. A second oxide portion is formed under the first oxide portion at a temperature above the threshold temperature. The substrate is illustratively oxidizable silicon and the threshold temperature is the viscoelastic temperature of silicon dioxide.
    Type: Application
    Filed: December 11, 2002
    Publication date: June 26, 2003
    Applicant: Agere Systems Inc.
    Inventors: Yuanning Chen, Sundar Srinivasan Chetlur, Pradip Kumar Roy
  • Patent number: 6576522
    Abstract: A method for deuterium sintering to improve the hot carrier aging of an integrated circuit includes (a) providing a partially fabricated integrated circuit structure comprising a semiconductor substrate and a dielectric layer formed on at least a portion of the substrate, the dielectric layer having at least one conductive material via plug formed therein and (b) sintering the structure in the presence of a gas comprising deuterium-containing components at high temperatures prior to a metallization layer being deposited on the structure.
    Type: Grant
    Filed: December 8, 2000
    Date of Patent: June 10, 2003
    Assignee: Agere Systems Inc.
    Inventors: Sundar Srinivasan Chetlur, Pradip Kumar Roy, Minesh Amrat Patel, Sidhartha Sen, Vivek Saxena
  • Patent number: 6551946
    Abstract: A process for forming an oxide layer includes forming a first oxide portion over a substrate at a temperature below a threshold temperature. A second oxide portion is formed under the first oxide portion at a temperature above the threshold temperature. The substrate is illustratively oxidizable silicon and the threshold temperature is the viscoelastic temperature of silicon dioxide.
    Type: Grant
    Filed: June 20, 2000
    Date of Patent: April 22, 2003
    Assignee: Agere Systems Inc.
    Inventors: Yuanning Chen, Sundar Srinivasan Chetlur, Pradip Kumar Roy
  • Patent number: 6552381
    Abstract: A trench capacitor formed on an SOI substrate extends through an upper silicon layer and an insulating layer and into a semiconductor base substrate. The outer electrode of the trench capacitor includes portions of the semiconductor base substrate which bound the trench in which the trench capacitor is formed. The outer electrode is coupled to a contact structure formed in close proximity to the trench capacitor, and which extends through the insulating layer. The method for simultaneously producing the trench capacitor and contact structure includes forming two trench openings, forming a dielectric liner on one of the trench openings, then filling each of the trench openings with a semiconductor material.
    Type: Grant
    Filed: February 5, 2002
    Date of Patent: April 22, 2003
    Assignee: Agere Systems, Inc.
    Inventors: Sailesh Chittipeddi, Charles Walter Pearce, Pradip Kumar Roy
  • Patent number: 6548854
    Abstract: A gate or capacitor insulator structure using a first grown oxide layer, a high-k dielectric material on the grown oxide layer, and a deposited oxide layer on the high-k dielectric material. The deposited oxide layer is preferably a densified deposited oxide layer. A conducting layer, such as a gate or capacitor plate, may overlay the densified oxide layer.
    Type: Grant
    Filed: December 22, 1997
    Date of Patent: April 15, 2003
    Assignee: Agere Systems Inc.
    Inventors: Isik C. Kizilyalli, Yi Ma, Pradip Kumar Roy
  • Patent number: 6541394
    Abstract: A method for making an oxide layer on a silicon substrate produces an oxide layer including graded portions with greatly reduced stress. The method includes growing a first oxide portion over a substrate by upwardly ramping the substrate to a first temperature lower than a SiO2 viscoelastic temperature. Thereafter a second oxide portion is grown between the first oxide portion and the silicon substrate by exposing the silicon substrate to an oxidizing ambient at a second temperature higher than the SiO2 viscoelastic temperature. The second oxide portion may have a thickness in a range of about 25 to 50% of a total thickness of the graded oxide layer.
    Type: Grant
    Filed: January 11, 2000
    Date of Patent: April 1, 2003
    Assignee: Agere Systems Guardian Corp.
    Inventors: Yuanning Chen, Sailesh Mansinh Merchant, Pradip Kumar Roy
  • Patent number: 6540974
    Abstract: Tantalum and niobium aluminate mixed metal oxides may be made by a process comprising mixing a first metal compound selected from the group consisting of aluminum alkoxide, aluminum beta-diketonate, aluminum alkoxide beta-diketonate, and mixtures thereof with a second metal compound selected from the group consisting of niobium alkoxide, niobium beta-diketonate, niobium alkoxide beta-diketonate, tantalum alkoxide, tantalum beta-diketonate, tantalum alkoxide beta-diketonate, and mixtures thereof to provide a precursor and then hydrolyzing the mixture. The resulting mixed metal oxide may be used in a variety of components of integrated circuits.
    Type: Grant
    Filed: July 27, 2001
    Date of Patent: April 1, 2003
    Assignee: Agere Systems Inc.
    Inventors: Sudhanshu Misra, Pradip Kumar Roy
  • Publication number: 20030054735
    Abstract: An improved polishing pad (22) for use in a chemical mechanical polishing (CMP) operation as part of a semiconductor device fabrication process. The polishing pad is formed of a plurality of particles of abrasive material (24) disposed in a matrix material (26). The abrasive particles may be a stiff inorganic material coated with a coupling agent, and the matrix material may be a polymeric material such as polyurethane. As the polishing pad wears through repeated polishing operations, the newly exposed polishing surface will contain fresh abrasive particles and will exhibit the same polishing properties as the original surface, thereby providing consistent polishing performance throughout the life of the pad without the need for conditioning operations. In one embodiment the distribution of particles of abrasive material per unit volume of matrix material may vary from one portion (23) of the pad to another (25).
    Type: Application
    Filed: September 17, 2001
    Publication date: March 20, 2003
    Inventors: Sudhanshu Misra, Pradip Kumar Roy
  • Patent number: 6535014
    Abstract: A tester for a circuit path includes a voltage controlled oscillator (VCO) for generating a controllable frequency oscillating test signal and having a controllable amplitude defined between first and second voltages, a multiplexer for selectively connecting one of the oscillating test signal, the first voltage, and the second voltage to the circuit path, and a selector for selectively connecting the multiplexer to the circuit path. Moreover, at least one of the first and second voltages may be controllable so that the VCO generates the oscillating test signal to selectively have one of an amplitude greater than, less than, and equal to an amplitude of an output of the circuit path. The circuit path may include a plurality of electronic circuit devices connected together.
    Type: Grant
    Filed: January 8, 2001
    Date of Patent: March 18, 2003
    Assignee: Lucent Technologies, Inc.
    Inventors: Sundar Srinivasan Chetlur, Pradip Kumar Roy