Abstract: A method for making an integrated circuit capacitor which in one embodiment preferably comprises the steps of: forming, adjacent a semiconductor substrate, a first metal electrode comprising a metal nitride surface portion; forming a tantalum pentoxide layer on the metal nitride surface portion while maintaining a temperature below an oxidizing temperature of the metal; remote plasma annealing the tantalum pentoxide layer; and forming a second electrode adjacent the tantalum pentoxide layer. The step of forming the tantalum pentoxide layer preferably comprises chemical vapor deposition of the tantalum pentoxide at a temperature below about 500° C. Accordingly, oxidation of the metal is avoided and a high quality tantalum pentoxide is produced. The metal of the first metal electrode may comprise at least one of titanium, tungsten, tantalum, and alloys thereof.

Abstract: An apparatus for determining the endpoint in a chemical mechanical polishing operation used for polishing a metal-containing material includes an electrochemical cell and an electronic circuit. An acidic polishing slurry is used to oxidize the metal and the oxidized metal is included in an effluent slurry stream, a sample of which is provided to the apparatus. The apparatus includes a liquid-phase working electrode, a reference electrode and a solid electrolyte which allows for the interchange of ions between the electrodes. An electronic circuit is coupled to the electrode for monitoring the component activity of the effluent slurry stream by measuring the electric potential across the electrodes. When the measured electric potential changes, indicating a change in the composition of the effluent slurry, endpoint is indicated.

Abstract: An integrated circuit capacitor includes a first dielectric layer adjacent a substrate and having a trench therein, and a metal plug comprising an upper portion extending upwardly into the trench, and a lower portion disposed in the first dielectric layer. The lower portion has a tapered width which increases in a direction toward the substrate to thereby secure the metal plug in the dielectric layer. Preferably, the upper portion is also tapered. Furthermore, a second dielectric layer is adjacent the metal plug with an upper electrode thereon.

Abstract: A method of fabricating an integrated circuit device includes forming a first metal oxide layer adjacent a semiconductor substrate. The first metal oxide layer may be formed of tantalum oxide, for example. A second metal oxide layer, which includes an oxide with a relatively high dielectric constant such as titanium oxide, zirconium oxide, or ruthenium oxide, is formed on the first metal oxide layer opposite the semiconductor substrate, and a metal nitride layer, such as titanium nitride, is formed on the metal oxide layer opposite the first metal oxide layer. The metal nitride layer includes a metal which is capable of reducing the metal oxide of the first metal oxide layer. Thus, the second metal oxide layer substantially blocks reduction of the metal oxide of the first metal oxide layer by the metal of the metal nitride layer.

Abstract: The present invention provides a method for fabricating a capacitor, comprising the steps of forming a trench in a substrate, forming a layer of a first material selected from the group consisting of titanium and titanium nitride in the trench, filling the trench with a conductive material to form a conductive plug, planarizing the substrate, patterning the substrate to partially expose the first material and to create a top portion and a bottom portion to the plug, wherein the bottom portion is in the substrate, and removing the first material from the top portion of the plug.

Abstract: A method for determining the endpoint in a chemical mechanical polishing operation used for polishing a metal-containing material. An acidic polishing slurry is used to oxidize the metal and the oxidized metal is included in an effluent slurry stream. The effluent slurry stream is directed into a vessel which forms an electrochemical cell. The component activity of the effluent slurry stream is monitored within the electrochemical cell by measuring the electric potential across the electrodes of the electrochemical cell. When the measured electric potential changes, indicating a change in the composition of the effluent slurry, endpoint is indicated.

Abstract: A method for making an oxide/nitride stacked layer makes the nitride layer defective so that it is semi-transparent or permeable to oxygen. The method includes first forming an oxide layer on a semiconductor substrate. The defective nitride layer is formed on the oxide layer using direct plasma enhanced chemical vapor deposition. The defective nitride layer is formed while exposing the plasma with a low energy magnetic field for providing a uniform energy distribution across a surface of the oxide layer. A resulting distribution of thicknesses of the defective nitride layer has a standard deviation less than about 1.5% across a wafer. The defective nitride layer is permeable to oxygen so that when the semiconductor substrate is annealed, the interface trap sites are significantly reduced or eliminated.

Abstract: A method of making a capacitor includes the steps of forming an interconnection line above a substrate, depositing a first dielectric layer on the interconnection line, and etching a via in the first dielectric layer. The via has a tapered width which increases in a direction toward the substrate. Further, the method includes filling the via with a conductive metal to form a metal plug, and etching a trench in the first dielectric layer around an upper portion of the metal plug. The metal plug has a tapered width which secures it into the dielectric layer. A second dielectric layer is deposited adjacent the metal plug and an upper electrode is deposited on the second dielectric layer. Preferably, a lower electrode is deposited to line the trench and contact the metal plug.

Abstract: A method for making a semiconductor device includes the steps of forming a first conductive layer adjacent a substrate, forming an etch stop layer on the conductive layer, and forming a dielectric layer on the etch stop layer. The dielectric layer includes a material having a low dielectric constant, and a via is formed through the dielectric layer to expose the etch stop layer at the bottom, with porous sidewalls being produced. The exposed etch stop layer is etched using an etchant that cooperates with etched material from the etch stop layer to form a polymeric layer to coat the porous sidewalls of the via. Since the etchant cooperates with the etched material from the etch stop layer to form the polymeric layer coating the porous sidewalls of the via, a separate coating layer deposition step is not required after the via is etched and cleaned.

Abstract: A CMOS gate structure comprises a multilayered polysilicon structure and a deposited silicide layer, with a nitridized silicide barrier layer formed therebetween. The multilayered polysilicon will exhibit a relatively large grain size and uniform structure. The deposited silicide layer is annealed to mimic the polysilicon grain size and structure. The combination of the tailored grain structure with the intermediate barrier layer results in a gate structure that is essentially impervious to subsequent dopant diffusions.

Abstract: A method of making a semiconductor device includes forming at least one opening, having vertical sidewalls and a bottom, in a first dielectric layer adjacent a substrate. A second dielectric layer is formed to line the vertical sidewalls of the at least one opening, and has a relatively lower etch rate than the first dielectric layer. A conductive layer is deposited to fill the at least one opening and an upper surface of the semiconductor wafer is cleaned. The method preferably includes the steps of depositing a barrier layer lining the second dielectric layer and the bottom of the at least one opening, and chemically mechanically polishing the semiconductor wafer with the second dielectric layer protecting upper edges of the barrier layer and conductive layer.

Abstract: A method for making an integrated circuit capacitor includes forming a first dielectric layer adjacent a substrate, forming a first opening in the first dielectric layer, filling the first opening with a conductive material to define a first metal plug, and forming a trench in the first dielectric layer adjacent the first metal plug. An interconnection line lines the first trench and contacts the first metal plug to define anchoring recesses on opposite sides of the first metal plug. The method further includes forming a second dielectric layer on the interconnection line, forming a second opening in the second dielectric layer, and filling the second opening with a conductive metal to define a second metal plug having a body portion and anchor portions extending downward from the body portion for engaging the anchoring recesses to anchor the second metal plug. A second trench is formed in the second dielectric layer adjacent the second metal plug, and is aligned with the first trench.

Abstract: The specification describes a process for making gate electrodes for silicon MOS transistor devices. The gate electrode is a composite of a first layer of tungsten suicide, a second layer of tungsten silicide nitride, and a third layer of tungsten silicide. The absence of polysilicon as a main constituent of the gate electrode eliminates depletion effects. The presence of nitride in the composite gate electrode impedes updiffusion of boron from the source and drain. The layers are preferably formed in situ in an PVD apparatus.

Abstract: Interconnects in porous dielectric materials are coated with a SiC-containing material to inhibit moisture penetration and retention within the dielectric material. Specifically, SiC coatings doped with boron such as SiC(BN) show particularly good results as barrier layers for dielectric interconnects.

Abstract: Undesirable birds beak pull back due to ion implant damage is alleviated by additional oxide growth.

Abstract: The specification describes intergate dielectrics between the floating silicon gate and the control silicon gate in MOS memory devices. The intergate dielectrics are composite structures of SiO.sub.2 --Ta.sub.2 O.sub.5 --SiO.sub.2 with the first SiO.sub.2 layer grown on the floating gate,, and all layers preferably produced in situ in an LPCVD reactor. After formation of the composite SiO.sub.2 --Ta.sub.2 O.sub.5 --SiO.sub.2 dielectric, it is annealed at low pressure to densify the SiO.sub.2 layers. Electrical measurements show that the charge trap density in the intergate dielectric is substantially lower than in layered dielectrics produced by prior techniques.

Abstract: A semiconductor device process for forming a multilayered nitride structure. The nitride is used as either isolation or as part of a dielectric structure. The deposition rate for the nitride is varied to form a multilayered structure with stress accommodation at the interface between sub-layers in the multilayer structure. In addition, the sub-layered structure reduces pin-holes and microcracks in the nitride film and improves the overall uniformity in thickness of the final nitride film.

Abstract: A composite 3-layer gate dielectric is disclosed. The upper and lower layers have a concentration of nitrogen atoms, while the middle layer has very few nitrogen atoms. The presence of the nitrogen atoms in the top sublayers provides resistance to boron diffusion from the top conductive layer and plasma damage during polysilicon gate stack formation and the presence of nitrogen in the bottom sublayer near the silicon-dielectric interface improves wearout, endurance, resistance to current stress and electron traps.

Abstract: A method of preventing diffusion penetration of the dopant used to dope polysilicon gate material in a MOSFET is disclosed. Atomic nitrogen is introduced into the substrate prior to gate oxide growth. The nitrogen later diffuses upward into the gate oxide and blocks subsequent ion implanted gate dopants from penetrating to the substrate. Low dosages of atomic nitrogen implantation, while not significantly affecting gate oxide growth rate, produce significant improvements in the damage immunity of thin gate oxides.

Abstract: A Si IC includes an Al-based layer which is deposited as a composite of sublayers of different composition Al-based materials. In one embodiment a first sublayer comprises an Al-Si-based alloy disposed so as to prevent substantial Si migration into the first sublayer, and a second sublayer, above the first, comprises an Al-based alloy with substantially no Si to alleviate precipitation-induced problems.