Abstract: Described herein is a memory bit-cell that results in lower leakage and higher sensing margin. In at least one embodiment, a memory bit-cell comprises a plurality of capacitors, wherein an individual capacitor is coupled to a node and an individual plate-line. In at least one embodiment, memory bit-cell comprises a first transistor coupled to the node. In at least one embodiment, memory bit-cell comprises a second transistor coupled in series with the first transistor, wherein the second transistor is coupled to a bit-line, wherein the first transistor or the second transistor is controllable by a word-line, and wherein the word-line is parallel to the individual plate-line.

Abstract: Described herein is a memory bit-cell that results in lower leakage and higher sensing margin. In at least one embodiment, a memory bit-cell comprises a plurality of capacitors, wherein an individual capacitor is coupled to a node and an individual plate-line. In at least one embodiment, memory bit-cell comprises a first transistor coupled to the node. In at least one embodiment, memory bit-cell comprises a second transistor coupled in series with the first transistor, wherein the second transistor is coupled to a bit-line, wherein the first transistor or the second transistor is controllable by a word-line, and wherein the word-line is parallel to the individual plate-line.

Abstract: Described herein is a memory bit-cell that results in lower leakage and higher sensing margin. In at least one embodiment, a memory bit-cell comprises a plurality of capacitors, wherein an individual capacitor is coupled to a node and an individual plate-line. In at least one embodiment, memory bit-cell comprises a first transistor coupled to the node. In at least one embodiment, memory bit-cell comprises a second transistor coupled in series with the first transistor, wherein the second transistor is coupled to a bit-line, wherein the first transistor or the second transistor is controllable by a word-line, and wherein the word-line is parallel to the individual plate-line.

Abstract: Described herein is a memory bit-cell that results in lower leakage and higher sensing margin. In at least one embodiment, a memory bit-cell comprises a plurality of capacitors, wherein an individual capacitor is coupled to a node and an individual plate-line. In at least one embodiment, memory bit-cell comprises a first transistor coupled to the node. In at least one embodiment, memory bit-cell comprises a second transistor coupled in series with the first transistor, wherein the second transistor is coupled to a bit-line, wherein the first transistor or the second transistor is controllable by a word-line, and wherein the word-line is parallel to the individual plate-line.

Abstract: Computer memory arrays employing memory banks and integrated serializer/de-serializer circuits for supporting serialization/de-serialization of read/write data in burst read/write modes, and related methods are disclosed. The memory array can include a serialization circuit configured to convert parallel data streams of read data received from separately switched memory banks into a single, serialized, read data stream in a burst read mode. The memory array can also include a de-serialization circuit configured to convert a received, serialized write data stream on an input bus for a write operation into separate, parallel write data streams to be written simultaneously to the memory banks in a burst write mode.

Abstract: Memory systems with burst mode having logic gates as sense elements and related methods are provided. A memory system comprises a memory array including a first set of memory cells coupled to a first wordline, a second set of memory cells coupled to a second wordline, and a plurality of sense elements, not including any sense amplifiers. The control unit is configured to generate control signals for: in response to a burst mode read request, simultaneously: (1) asserting a first wordline signal on the first wordline coupled to each of a plurality of first set of bitlines, and (2) asserting a second wordline signal on the second wordline coupled to each of a plurality of second set of bitlines, and as part of a burst, outputting data corresponding to a subset of each of the first set of memory cells and the second set of memory cells.

Abstract: Described herein is a memory bit-cell that results in lower leakage and higher sensing margin. In at least one embodiment, a memory bit-cell comprises a plurality of capacitors, wherein an individual capacitor is coupled to a node and an individual plate-line. In at least one embodiment, memory bit-cell comprises a first transistor coupled to the node. In at least one embodiment, memory bit-cell comprises a second transistor coupled in series with the first transistor, wherein the second transistor is coupled to a bit-line, wherein the first transistor or the second transistor is controllable by a word-line, and wherein the word-line is parallel to the individual plate-line.

Abstract: Memory arrays employing flying bit lines to increase effective bit line length for supporting higher performance, increased memory density, and related methods. To increase memory density, the memory array has a first memory sub-bank and one or more second memory sub-banks. The first memory sub-bank includes a first bit line(s) for each of its memory column circuits. To avoid the need to extend the length of the first bit lines to be coupled to the second memory bit cells in the second memory sub-bank, each memory sub-bank has its own dedicated first and second bit lines coupling their respective memory bit cells to access circuitry. The second bit lines effectively “fly” independent of the first bit lines of the first memory sub-bank. The first bit lines of the first memory sub-bank do not have to be extended in length to provide bit lines for the second memory sub-bank.

Abstract: Computer memory arrays employing memory banks and integrated serializer/de-serializer circuits for supporting serialization/de-serialization of read/write data in burst read/write modes, and related methods are disclosed. The memory array can include a serialization circuit configured to convert parallel data streams of read data received from separately switched memory banks into a single, serialized, read data stream in a burst read mode. The memory array can also include a de-serialization circuit configured to convert a received, serialized write data stream on an input bus for a write operation into separate, parallel write data streams to be written simultaneously to the memory banks in a burst write mode.

Abstract: A refreshable braille display device is provided comprising a plurality of Braille pins running through a perforated body of the reader, the pins arranged in the spacing and order of Braille dots of standard Braille cells. The Braille reader may be coupled to a device for Braille text generation via selective hammering or impacting of Braille pins. From a default position where all pins of the reader are raised relative to a first, front surface of the reader, one or more pins are selectively impacted in a sequence to create a Braille pattern of raised and lowered pins based on a desired text conversion.

Abstract: Memory arrays employing flying bit lines to increase effective bit line length for supporting higher performance, increased memory density, and related methods. To increase memory density, the memory array has a first memory sub-bank and one or more second memory sub-banks. The first memory sub-bank includes a first bit line(s) for each of its memory column circuits. To avoid the need to extend the length of the first bit lines to be coupled to the second memory bit cells in the second memory sub-bank, each memory sub-bank has its own dedicated first and second bit lines coupling their respective memory bit cells to access circuitry. The second bit lines effectively “fly” independent of the first bit lines of the first memory sub-bank. The first bit lines of the first memory sub-bank do not have to be extended in length to provide bit lines for the second memory sub-bank.

Abstract: Memory systems with burst mode having logic gates as sense elements and related methods are provided. A memory system comprises a memory array including a first set of memory cells coupled to a first wordline, a second set of memory cells coupled to a second wordline, and a plurality of sense elements, not including any sense amplifiers. The control unit is configured to generate control signals for: in response to a burst mode read request, simultaneously: (1) asserting a first wordline signal on the first wordline coupled to each of a plurality of first set of bitlines, and (2) asserting a second wordline signal on the second wordline coupled to each of a plurality of second set of bitlines, and as part of a burst, outputting data corresponding to a subset of each of the first set of memory cells and the second set of memory cells.

Abstract: A memory array for storing odd and even data bits of data words in alternate sub-banks to reduce multi-bit error rate is disclosed. The memory array alternates odd data bits of a first plurality of data words in consecutive columns a first sub-bank of first and second memory banks and even data bits of the first plurality of data words in consecutive columns of a second sub-bank of the first and second memory banks. For example, the lowest bits of each of N data words are stored in a first N consecutive columns of a first sub-bank. The second bits of the N data words are stored in the next N consecutive columns of a second sub-bank. The N data bits in each of the bit positions of the N data words are interleaved in corresponding column mux sets. Alternating odd and even bits between sub-banks reduces multi-bit soft errors.

Abstract: Memory systems with burst mode having logic gates as sense elements and related methods are provided. A memory system comprises a memory array including a first set of memory cells coupled to a first wordline, a second set of memory cells coupled to a second wordline, and a plurality of sense elements, not including any sense amplifiers. The control unit is configured to generate control signals for: in response to a burst mode read request, simultaneously: (1) asserting a first wordline signal on the first wordline coupled to each of a plurality of first set of bitlines, and (2) asserting a second wordline signal on the second wordline coupled to each of a plurality of second set of bitlines, and as part of a burst, outputting data corresponding to a subset of each of the first set of memory cells and the second set of memory cells.

Abstract: Memory systems having flying bitlines for improved burst mode read operations and related methods are provided. A memory system comprises a memory array including a first set of memory cells coupled to a first inner wordline and a second set of memory cells coupled to a first outer wordline. The memory system includes a control unit configured to generate control signals for simultaneously: asserting a first wordline signal on the first inner wordline coupled to each of a plurality of inner bitlines, and asserting a second wordline signal on the first outer wordline coupled to each of a plurality of outer bitlines, where each of the plurality of outer bitlines includes a first portion configured to fly over or fly under a corresponding inner bitline, and outputting data from each of the first set of memory cells and the second set of memory cells as part of a burst.

Abstract: A refreshable braille display device is provided comprising a plurality of Braille pins running through a perforated body of the reader, the pins arranged in the spacing and order of Braille dots of standard Braille cells. The Braille reader may be coupled to a device for Braille text generation via selective hammering or impacting of Braille pins. From a default position where all pins of the reader are raised relative to a first, front surface of the reader, one or more pins are selectively impacted in a sequence to create a Braille pattern of raised and lowered pins based on a desired text conversion.

Abstract: Memory systems having flying bitlines for improved burst mode read operations and related methods are provided. A memory system comprises a memory array including a first set of memory cells coupled to a first inner wordline and a second set of memory cells coupled to a first outer wordline. The memory system includes a control unit configured to generate control signals for simultaneously: asserting a first wordline signal on the first inner wordline coupled to each of a plurality of inner bitlines, and asserting a second wordline signal on the first outer wordline coupled to each of a plurality of outer bitlines, where each of the plurality of outer bitlines includes a first portion configured to fly over or fly under a corresponding inner bitline, and outputting data from each of the first set of memory cells and the second set of memory cells as part of a burst.

Abstract: Memory systems with burst mode having logic gates as sense elements and related methods are provided. A memory system comprises a memory array including a first set of memory cells coupled to a first wordline, a second set of memory cells coupled to a second wordline, and a plurality of sense elements, not including any sense amplifiers. The control unit is configured to generate control signals for: in response to a burst mode read request, simultaneously: (1) asserting a first wordline signal on the first wordline coupled to each of a plurality of first set of bitlines, and (2) asserting a second wordline signal on the second wordline coupled to each of a plurality of second set of bitlines, and as part of a burst, outputting data corresponding to a subset of each of the first set of memory cells and the second set of memory cells.

Abstract: A memory array for storing odd and even data bits of data words in alternate sub-banks to reduce multi-bit error rate is disclosed. The memory array alternates odd data bits of a first plurality of data words in consecutive columns a first sub-bank of first and second memory banks and even data bits of the first plurality of data words in consecutive columns of a second sub-bank of the first and second memory banks. For example, the lowest bits of each of N data words are stored in a first N consecutive columns of a first sub-bank. The second bits of the N data words are stored in the next N consecutive columns of a second sub-bank. The N data bits in each of the bit positions of the N data words are interleaved in corresponding column mux sets. Alternating odd and even bits between sub-banks reduces multi-bit soft errors.

Abstract: A refreshable braille display device is provided comprising a plurality of Braille pins running through a perforated body of the reader, the pins arranged in the spacing and order of Braille dots of standard Braille cells. The Braille reader may be coupled to a device for Braille text generation via selective hammering or impacting of Braille pins. From a default position where all pins of the reader are raised relative to a first, front surface of the reader, one or more pins are selectively impacted in a sequence to create a Braille pattern of raised and lowered pins based on a desired text conversion.