Abstract: A static random-access memory is described. The SRAM includes a storage cell and a voltage supply to supply the storage cell with a reduced voltage during a write operation. The SRAM cell includes a first pass gate and a second pass gate. A first resistor is coupled between the first pass gate and a first side of the storage cell. A second resistor is coupled between the second pass gate and a second side of the storage cell.

Abstract: In one embodiment, a memory cell circuit for storing data includes a pair of cross-coupled inverters for storing states of the memory cell circuit. Access devices provide access to the pair of cross-coupled inverters. The memory cell circuit also includes a set of electrically inactive p-type metal oxide semiconductor (PMOS) devices that are coupled to the pair of cross-coupled inverters. The set of electrically inactive PMOS devices in combination with a portion (e.g., PMOS devices) of the pair of cross-coupled inverters enables a continuous p-type diffusion layer for the memory cell circuit.

Abstract: In some embodiments, disclosed is a wordline boosting technique using a self-timed capacitive charge boosting approach.

Abstract: A negative bitline write assist circuit includes a bias capacitor configured to facilitate driving the capacitance of a bitline. The negative bitline write assist circuit may be modularly replicated within a circuit to change the amount of negative voltage on the bitline during write operations. The bitline write assist circuit may be coupled directly to the bitline, removing the need to add a pull-down transistor to the write driver.

Abstract: A negative bitline write assist circuit includes a bias capacitor configured to facilitate driving the capacitance of a bitline. The negative bitline write assist circuit may be modularly replicated within a circuit to change the amount of negative voltage on the bitline during write operations. The bitline write assist circuit may be coupled directly to the bitline, removing the need to add a pull-down transistor to the write driver.

Abstract: In one embodiment, a memory cell circuit for storing data includes a pair of cross-coupled inverters for storing states of the memory cell circuit. Access devices provide access to the pair of cross-coupled inverters. The memory cell circuit also includes a set of electrically inactive p-type metal oxide semiconductor (PMOS) devices that are coupled to the pair of cross-coupled inverters. The set of electrically inactive PMOS devices in combination with a portion (e.g., PMOS devices) of the pair of cross-coupled inverters enables a continuous p-type diffusion layer for the memory cell circuit.

Abstract: In one embodiment, a memory cell circuit for storing data includes a pair of cross-coupled inverters for storing states of the memory cell circuit. Access devices provide access to the pair of cross-coupled inverters. The memory cell circuit also includes a set of electrically inactive p-type metal oxide semiconductor (PMOS) devices that are coupled to the pair of cross-coupled inverters. The set of electrically inactive PMOS devices in combination with a portion (e.g., PMOS devices) of the pair of cross-coupled inverters enables a continuous p-type diffusion layer for the memory cell circuit.

Abstract: In one embodiment, a memory cell circuit for storing data includes a pair of cross-coupled inverters for storing states of the memory cell circuit. Access devices provide access to the pair of cross-coupled inverters. The memory cell circuit also includes a set of electrically inactive p-type metal oxide semiconductor (PMOS) devices that are coupled to the pair of cross-coupled inverters. The set of electrically inactive PMOS devices in combination with a portion (e.g., PMOS devices) of the pair of cross-coupled inverters enables a continuous p-type diffusion layer for the memory cell circuit.

Abstract: A negative bitline write assist circuit includes a bias capacitor configured to facilitate driving the capacitance of a bitline. The negative bitline write assist circuit may be modularly replicated within a circuit to change the amount of negative voltage on the bitline during write operations. The bitline write assist circuit may be coupled directly to the bitline, removing the need to add a pull-down transistor to the write driver.

Abstract: A static random-access memory is described. The SRAM includes a storage cell and a voltage supply to supply the storage cell with a reduced voltage during a write operation. The SRAM cell includes a first pass gate and a second pass gate. A first resistor is coupled between the first pass gate and a first side of the storage cell. A second resistor is coupled between the second pass gate and a second side of the storage cell.

Abstract: Adaptive and dynamic stability enhancement for memories is described. In one example, the enhancement includes a plurality of sensors each located near a plurality of memory cells to provide a sensor voltage, a controller to receive the sensor voltage and provide a control signal based thereon, and a read/write assist circuit coupled to the controller to adjust a parameter applied to reading from and writing to a memory cell of the plurality of memory cells in response to the control signal.

Abstract: Adaptive and dynamic stability enhancement for memories is described. In one example, the enhancement includes a plurality of sensors each located near a plurality of memory cells to provide a sensor voltage, a controller to receive the sensor voltage and provide a control signal based thereon, and a read/write assist circuit coupled to the controller to adjust a parameter applied to reading from and writing to a memory cell of the plurality of memory cells in response to the control signal.

Abstract: Low-power, all-p-channel enhancement-type metal-oxide semiconductor field-effect transistor (PMOSFET) SRAM cells are disclosed. A PMOSFET SRAM cell is disclosed. The SRAM cell can include a latch having first and second PMOSFETs for storing data. Further, a gate of the first PMOSFET is connected to a drain of the second PMOSFET at a first memory node. A gate of the second PMOSFET is connected to a drain of the first PMOSFET at a second memory node. The SRAM cell can also include third and fourth PMOSFETs forming a pull-down circuit. A source of the third PMOSFET is connected to the first memory node. Further, a source of the fourth PMOSFET is connected to the second memory node. The SRAM cell can include access circuitry for accessing data at the first and second memory nodes for read or write operations.

Abstract: Low-power, all-p-channel enhancement-type metal-oxide semiconductor field-effect transistor (PMOSFET) SRAM cells. A PMOSFET SRAM cell is disclosed. The SRAM cell can include a latch having first and second PMOSFETs for storing data. Further, a gate of the first PMOSFET is connected to a drain of the second PMOSFET at a first memory node. A gate of the second PMOSFET is connected to a drain of the first PMOSFET at a second memory node. The SRAM cell can also include third and fourth PMOSFETs forming a pull-down circuit. A source of the third PMOSFET is connected to the first memory node. Further, a source of the fourth PMOSFET is connected to the second memory node. The SRAM cell can include access circuitry for accessing data at the first and second memory nodes for read or write operations.

Abstract: An apparatus for actuating a droplet comprises a first conductive layer, a second conductive layer, a conductive elongate element, and a voltage source. The first conductive layer comprises a first hydrophobic surface. The second conductive layer comprises a hydrophilic surface facing the first hydrophobic surface. The second conductive layer is axially spaced from the first conductive layer to define a gap therebetween. The conductive medial element is disposed in the gap between the first and second conductive layers, and comprises a second hydrophobic surface. The voltage source communicates with the second conductive layer and the elongate element. By applying a voltage potential between the elongate element and the second conductive layer, droplets can be electrostatically actuated so as to move from the first conductive layer into contact with the second conductive layer. The apparatus is particularly useful in the synthesis of microarrays of biological, chemical, or biochemical samples.

Abstract: An apparatus for actuating a droplet comprises a first conductive layer, a second conductive layer, a conductive elongate element, and a voltage source. The first conductive layer comprises a first hydrophobic surface. The second conductive layer comprises a hydrophilic surface facing the first hydrophobic surface. The second conductive layer is axially spaced from the first conductive layer to define a gap therebetween. The conductive medial element is disposed in the gap between the first and second conductive layers, and comprises a second hydrophobic surface. The voltage source communicates with the second conductive layer and the elongate element. By applying a voltage potential between the elongate element and the second conductive layer, droplets can be electrostatically actuated so as to move from the first conductive layer into contact with the second conductive layer. The apparatus is particularly useful in the synthesis of microarrays of biological, chemical, or biochemical samples.