Patents by Inventor Pramod Kumar

Pramod Kumar has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 12220688
    Abstract: The present invention provides a novel, cost-effective and simple synthetic process for preparing a nano ZSM-5 catalyst which is further utilized in fluid catalytic cracking of feedstock oil containing organic compounds. The nano-ZSM-5 catalyst shows higher selectivity towards olefines and low selectivity towards LCO and bottoms.
    Type: Grant
    Filed: March 30, 2023
    Date of Patent: February 11, 2025
    Inventors: Narasimharao Kanna, Suresh Kumar B, Hemant Mishra, Pramod Kumar
  • Publication number: 20250047690
    Abstract: An apparatus includes at least one processing device configured to determine, for endpoint nodes of a distributed processing system, node security information characterizing security issues encountered on one or more of the endpoint nodes. The processing device is also configured to identify, based on the node security information, a first type of security issues encountered on a first endpoint node and a second type of security issues encountered on a second endpoint node. The processing device is further configured to select first and second sets of corrective actions for the first and second types of security issues. The processing device is further configured to apply, to the first endpoint node, the first set of corrective actions, and to apply the second set of corrective actions by deploying an additional endpoint node in the distributed processing system and migrating workloads running on the second endpoint node to the additional endpoint node.
    Type: Application
    Filed: August 2, 2023
    Publication date: February 6, 2025
    Inventors: Pramod Kumar Puthanveettil Kurungodan, Peniel Charles, Manikandan Sethuraman
  • Patent number: 12209553
    Abstract: The present disclosure relates to an engine (100) including a cylinder (102) that is filled with carbon dioxide. A first piston (104) is slidably configured inside the cylinder (102) and being configured to form a first cylinder (108) with a first end (130) of the cylinder (102). A second piston (106) is slidably configured inside the cylinder (102) and being configured to form a second cylinder (110) with a second end (132) of the cylinder (102). A heater (112) is circumferentially disposed around the first cylinder (108) and the first piston (104) is configured to expand a hot carbon dioxide received inside the first cylinder (108) from the heater (112). A cooler (116) is circumferentially disposed around the second cylinder (110) and second piston (104) is configured to compress a cold carbon dioxide received inside the second cylinder (110) from the cooler (116).
    Type: Grant
    Filed: December 28, 2021
    Date of Patent: January 28, 2025
    Assignee: INDIAN INSTITUTE OF SCIENCE
    Inventors: Pramod Kumar, Siddhant Karmarkar, Vijay Biradar
  • Patent number: 12206400
    Abstract: A radio frequency integrated circuit (RFIC) is described. The RFIC includes a switch field effect transistor (FET). The switch FET includes a source region, a drain region, a body region, and a gate region. The RFIC also includes a dynamic bias control circuit. The dynamic bias control circuit includes at least one transistor coupled between the body region and the gate region of the switch FET.
    Type: Grant
    Filed: August 22, 2022
    Date of Patent: January 21, 2025
    Assignee: QUALCOMM INCORPORATED
    Inventors: Ravi Pramod Kumar Vedula, Abhijeet Paul, Hyunchul Jung
  • Publication number: 20250021481
    Abstract: An apparatus includes first CPU and second CPU cores, a L1 cache subsystem coupled to the first CPU core and comprising a L1 controller, and a L2 cache subsystem coupled to the L1 cache subsystem and to the second CPU core. The L2 cache subsystem includes a L2 memory and a L2 controller configured to operate in an aliased mode in response to a value in a memory map control register being asserted. In the aliased mode, the L2 controller receives a first request from the first CPU core directed to a virtual address in the L2 memory, receives a second request from the second CPU core directed to the virtual address in the L2 memory, directs the first request to a physical address A in the L2 memory, and directs the second request to a physical address B in the L2 memory.
    Type: Application
    Filed: August 8, 2024
    Publication date: January 16, 2025
    Inventors: Abhijeet Ashok Chachad, Timothy David Anderson, Pramod Kumar Swami, Naveen Bhoria, David Matthew Thompson, Neelima Muralidharan
  • Publication number: 20250002458
    Abstract: The present disclosure is directed to salt forms of nicorandil derivatives, pharmaceutical compositions thereof, and methods of using the salt forms and pharmaceutical compositions for treating diseases or conditions.
    Type: Application
    Filed: May 23, 2024
    Publication date: January 2, 2025
    Inventors: Pramod Kumar GUPTA, Shalabh GUPTA
  • Patent number: 12184840
    Abstract: This invention predicts that intra mode prediction is more effective for the macroblocks where motion estimation in inter mode prediction fails. This failure is indicated by a large value of the inter mode SAD. This invention performs intra mode prediction for only macro blocks have larger inter mode SADs. The definition of a large inter mode SAD differs for different content. This invention compares the inter mode SAD of a current macroblock with an adaptive threshold. This adaptive threshold depends on the average and variance of the SADs of the previous predicted frame. An adaptive threshold is calculated for each new predictive frame.
    Type: Grant
    Filed: July 27, 2022
    Date of Patent: December 31, 2024
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Soyeb Nagori, Manu Mathew, Pramod Kumar Swami
  • Publication number: 20240408270
    Abstract: An implant imaging system (200) is disclosed. The implant imaging system 200 may be provided on a joint implant made of polymer. The implant imaging system (200) includes one or more metal plates (212) including at least one bone contacting surface ‘B’. The metal plates (212) are disposed on a joint implant. Further, the bone contacting surface ‘B’ metal plates (212) are coated with one or more coatings of osteoconductive material. The presence of osteoconductive material increases the rate of osteointegration of the joint implant.
    Type: Application
    Filed: February 24, 2022
    Publication date: December 12, 2024
    Applicant: MERIL HEALTHCARE PVT. LTD
    Inventors: PRAMOD KUMAR MINOCHA, DEVESHKUMAR MAHENDRALAL KOTHWALA, ARPIT PRADIPKUMAR DAVE
  • Publication number: 20240394543
    Abstract: In an example, a method includes executing, using one or more processors, a power-of-2 parametric activation (PACT2) function to quantize a set of data. The executing of the PACT2 function includes determining a distribution for the set of data; discarding a portion of the data corresponding to a tail of the distribution to form a remaining set of data; estimating a maximum value of the remaining set of data; determining a new maximum value of the remaining set of data using a moving average and at least one historical value of at least one prior remaining set of data; determining a clipping value by expanding the new maximum value to a nearest power of two value; and quantizing the set of data using the clipping value to form a quantized set of data.
    Type: Application
    Filed: August 6, 2024
    Publication date: November 28, 2024
    Inventors: Manu Mathew, Kumar Desappan, Soyeb Noormohammed Nagori, Debapriya Maji, Pramod Kumar Swami
  • Patent number: 12155381
    Abstract: A radio frequency (RF) device is described. The RF device includes a switch field effect transistor (FET), having a source region, a drain region, a body region, and a gate region. The RF device also includes a dynamic bias control circuit. The dynamic bias control circuit includes a first transistor coupled to the gate region of the switch FET by a gate resistor. The dynamic bias control circuit also includes a second transistor coupled to the first transistor and coupled to the body region of the switch FET by a body resistor. The dynamic bias control circuit further includes a capacitor coupled to the body region of the switch FET by the body resistor, and the gate region of the switch FET, by the gate resistor.
    Type: Grant
    Filed: February 1, 2023
    Date of Patent: November 26, 2024
    Assignee: QUALCOMM INCORPORATED
    Inventors: Ravi Pramod Kumar Vedula, Abhijeet Paul, Hyunchul Jung
  • Patent number: 12123253
    Abstract: A configurable door system includes a first and second door panel, an astragal, and a frame. The frame defines a first axis and is configured to pivotally support the door panels in a first configuration of the door system and in a second configuration of the door system. The first door panel is disposed to one side of the second door panel along the first axis within the frame in both the first and second configurations. The door system, in the first configuration, includes the astragal fixed to the first door panel and releasably attaches the first door panel to the frame, and the second door panel is releasably secured to the astragal. The door system, in the second configuration, includes the astragal fixed to the second door panel and releasably attaches the second door panel to the frame, and the first door panel is releasably secured to the astragal.
    Type: Grant
    Filed: October 27, 2022
    Date of Patent: October 22, 2024
    Inventors: Andres Ortega, Pramod Kumar, Garrick Beat, Jacob Chan
  • Patent number: 12124715
    Abstract: Disclosed are various embodiments for improving resiliency and performance of clustered memory. A computing device can acquire a chunk of byte-addressable memory from a cluster memory host. The computing device can then identify an active set of allocated memory pages and an inactive set of allocated memory pages for a process executing on the computing device. Next, the computing device can store the active set of allocated memory pages for the process in the memory of the computing device. Finally, the computing device can store the inactive set of allocated memory pages for the process in the chunk of byte-addressable memory of the cluster memory host.
    Type: Grant
    Filed: May 24, 2023
    Date of Patent: October 22, 2024
    Assignee: VMware LLC
    Inventors: Marcos K. Aguilera, Keerthi Kumar, Pramod Kumar, Pratap Subrahmanyam, Sairam Veeraswamy, Rajesh Venkatasubramanian
  • Publication number: 20240321729
    Abstract: Disclosed is an integrated circuit (IC) with an inductor formed from redistribution layers (RDLs). An airgap is provided in an interlayer dielectric (ILD) under the bottom most RDL that makes up the inductor. In this way, an inductor with high Q value is achieved. Also, inductor isolation is improved. Thus, circuits may be placed under the inductor resulting is a smaller die.
    Type: Application
    Filed: March 20, 2023
    Publication date: September 26, 2024
    Inventors: Abhijeet PAUL, Ravi Pramod Kumar VEDULA, Yufei WU
  • Publication number: 20240320045
    Abstract: Techniques for executing machine learning (ML) models including receiving an indication to run an ML model on a processing core; receiving a static memory allocation for running the ML model on the processing core; determining that a layer of the ML model uses more memory than the static memory allocated; transmitting, to a shared memory, a memory request for blocks of the shared memory; receiving an allocation of the requested blocks; running the layer of the ML model using the static memory and the range of memory addresses; and outputting results of running the layer of the ML model.
    Type: Application
    Filed: May 28, 2024
    Publication date: September 26, 2024
    Inventors: Mihir Narendra MODY, Kedar Satish CHITNIS, Kumar DESAPPAN, David SMITH, Pramod Kumar SWAMI, Shyam JAGANNATHAN
  • Publication number: 20240318554
    Abstract: The present disclosure relates to an engine (100) including a cylinder (102) that is filled with carbon dioxide. A first piston (104) is slidably configured inside the cylinder (102) and being configured to form a first cylinder (108) with a first end (130) of the cylinder (102). A second piston (106) is slidably configured inside the cylinder (102) and being configured to form a second cylinder (110) with a second end (132) of the cylinder (102). A heater (112) is circumferentially disposed around the first cylinder (108) and the first piston (104) is configured to expand a hot carbon dioxide received inside the first cylinder (108) from the heater (112). A cooler (116) is circumferentially disposed around the second cylinder (110) and second piston (104) is configured to compress a cold carbon dioxide received inside the second cylinder (110) from the cooler (116).
    Type: Application
    Filed: December 28, 2021
    Publication date: September 26, 2024
    Inventors: Pramod KUMAR, Siddhant KARMARKAR, Vijay BIRADAR
  • Patent number: 12099930
    Abstract: In described examples of a method for quantizing data for a convolutional neural network (CNN) is provided. A set of data is received and quantized the using a power-of-2 parametric activation (PACT2) function. The PACT2 function arranges the set of data as a histogram and discards a portion of the data corresponding to a tail of the histogram to form a remaining set of data. A clipping value is determined by expanding the remaining set of data to a nearest power of two value. The set of data is then quantized using the clipping value. With PACT2, a model can be quantized either using post training quantization or using quantization aware training. PACT2 helps a quantized model to achieve close accuracy compared to the corresponding floating-point model.
    Type: Grant
    Filed: December 10, 2020
    Date of Patent: September 24, 2024
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Manu Mathew, Kumar Desappan, Soyeb Noormohammed Nagori, Debapriya Maji, Pramod Kumar Swami
  • Patent number: 12086064
    Abstract: An apparatus includes first CPU and second CPU cores, a L1 cache subsystem coupled to the first CPU core and comprising a L1 controller, and a L2 cache subsystem coupled to the L1 cache subsystem and to the second CPU core. The L2 cache subsystem includes a L2 memory and a L2 controller configured to operate in an aliased mode in response to a value in a memory map control register being asserted. In the aliased mode, the L2 controller receives a first request from the first CPU core directed to a virtual address in the L2 memory, receives a second request from the second CPU core directed to the virtual address in the L2 memory, directs the first request to a physical address A in the L2 memory, and directs the second request to a physical address B in the L2 memory.
    Type: Grant
    Filed: June 22, 2022
    Date of Patent: September 10, 2024
    Assignee: Texas Instruments Incorporated
    Inventors: Abhijeet Ashok Chachad, Timothy David Anderson, Pramod Kumar Swami, Naveen Bhoria, David Matthew Thompson, Neelima Muralidharan
  • Patent number: 12086469
    Abstract: Disclosed are various embodiments for improving the resiliency and performance for clustered memory. A computing device can mark a page of the memory as being reclaimed. The computing device can then set the page of the memory as read-only. Next, the computing device can submit a write request for the contents of the page to individual ones of a plurality of memory hosts. Subsequently, the computing device can receive individual confirmations of a successful write of the page from the individual ones of the plurality of memory hosts. Then, the computing device can mark the page as free in response to receipt of the individual confirmations of the successful write from the individual ones of the plurality of memory hosts.
    Type: Grant
    Filed: May 5, 2023
    Date of Patent: September 10, 2024
    Assignee: VMware LLC
    Inventors: Marcos K. Aguilera, Keerthi Kumar, Pramod Kumar, Pratap Subrahmanyam, Sairam Veeraswamy, Rajesh Venkatasubramanian
  • Publication number: 20240271375
    Abstract: Composite decks increase bridge strength and stiffness. Prestressed composite open web steel girder has added advantage of high strength cable support. Results of typical 125 m span bridges having heights of 9.0 m, 10.0 m and 12.5 m, and another 50.0 m span and 2.5 m height are given. Member stresses and bridge deflections during erection remained safe. Average steel off take for the 125 m bridge is 2.65 t/m and for the 50 m span bridge it is 1.77 t/m for limiting live load deflection of Span/800. Its reserve strength is 3.2 times service condition live load. The girders are panel wise workshop fabricated, assembled at site, jacked up or crane lifted to secure over bearings. Connection of the cross members, and onsite deck casting in parts with stage wise bottom chord prestressing is carried out. Short to long span bridges for single or multiple lanes in road, rail, metro rail, and coastal link projects are feasible.
    Type: Application
    Filed: August 25, 2023
    Publication date: August 15, 2024
    Inventor: Pramod Kumar Singh
  • Publication number: 20240253027
    Abstract: The present invention provides a novel, cost-effective and simple synthetic process for preparing a nano ZSM-5 catalyst which is further utilized in fluid catalytic cracking of feedstock oil containing organic compounds. The nano-ZSM-5 catalyst shows higher selectivity towards olefines and low selectivity towards LCO and bottoms.
    Type: Application
    Filed: March 30, 2023
    Publication date: August 1, 2024
    Inventors: Narasimharao KANNA, Suresh Kumar B, Hemant MISHRA, Pramod KUMAR