Abstract: Methods and systems are described to efficiently identify the potential for failures in integrated circuits (ICs) caused by glitches. In an IC based on synchronous operation, the operation of the multiplicity of inputs, storage elements and observed outputs in said IC are synchronized to one or more clocks that determine the specific times at which inputs change, outputs are observed, and stored values are updated. Almost all ICs are based on synchronous operation. When input values to a logic circuit in an IC change, the effects of said changes propagate through paths in said logic circuit in a delayed manner such that each of said paths may have a different delay. Said different delays can cause a wire in a logic circuit to have transient values (termed “glitch”) before settling to a final value consistent with the input values being applied to said logic circuit.

Abstract: Methods and systems are described to augment gate-level simulation with the ability to efficiently detect and correct X-pessimism on-the-fly. Using static Boolean analysis, gates are identified in the simulated hardware where there is potential for the simulator to propagate an X while the actual hardware propagates a 1 or 0, i.e. gates where X-pessimism potentially occurs. Data regarding potentially pessimistic gates is utilized in real time during simulation to determine actual pessimism at the gate and to correct it when it happens. Whereas the understanding of X-pessimism and the method of augmenting simulation with attributes to correct X-pessimism in simulation on-the-fly is known in the public domain preceding known patents, various methods have been proposed recently to make on-the-fly X-pessimism correction more efficient for large ICs. The methods and systems described in the present invention, achieve new levels of performance and scalability of X-pessimism detection and correction.

Abstract: Methods and systems are described to augment gate-level simulation with the ability to efficiently detect and correct X-pessimism on-the-fly. Using static Boolean analysis, gates are identified in the simulated hardware where there is potential for the simulator to propagate an X while the actual hardware propagates a 1 or 0, i.e. gates where X-pessimism potentially occurs. Data regarding potentially pessimistic gates is utilized in real time during simulation to determine actual pessimism at the gate and to correct it when it happens. Whereas the understanding of X-pessimism and the method of augmenting simulation with attributes to correct X-pessimism in simulation on-the-fly is known in the public domain preceding known patents, various methods have been proposed recently to make on-the-fly X-pessimism correction more efficient for large ICs. The methods and systems described in the present invention, achieve new levels of performance and scalability of X-pessimism detection and correction.

Abstract: A system and method is disclosed for formal verification of software programs that advantageously bounds the ranges of values that a variable in the software can take during runtime.

Abstract: A method of obtaining a resolution-based proof of unsatisfiability using a SAT procedure for a hybrid Boolean constraint problem comprising representing constraints as a combination of clauses and interconnected gates. The proof is obtained as a combination of clauses, circuit gates and gate connectivity constraints sufficient for unsatisfiability.

Abstract: A method for bounded model checking of arbitrary Linear Time Logic temporal properties. The method comprises translating properties associated with temporal operators F(p), G(p), U(p, q) and X(p) into property checking schemas comprising Boolean satisfiability checks, wherein F represents an eventuality operator, G represents a globally operator, U represents an until operator and X represents a next-time operator. The overall property is checked in a customized manner by repeated invocations of the property checking schemas for F(p), G(p), U(p, q), X(p) operators and standard handling of atomic propositions and Boolean operators.

Abstract: A computer-implemented method for augmenting SAT-based BMC to handle embedded memory designs without explicitly modeling memory bits. As is known, verifying designs having large embedded memories is typically handled by abstracting out (over-approximating) the memories. Such abstraction is not useful for finding real bugs. SAT-based BMC, as of now, is incapable of handling designs with explicit memory modeling due to enormously increased search space complexity. Advantageously, our method does not require analyzing the designs and also guarantees not to generate false negatives.

Abstract: A method of checking correctness of scheduling of a circuit where a schedule for the circuit is obtained from a behavioral description. The method comprising extracting loop invariants to determine a sufficient set of acyclic threads when loops are present, performing symbolic simulation to extract the above loop invariants, and proving equivalence of the acyclic threads. Systems, computer systems and computer program products that incorporate the techniques of verification and correctness checking according to the present invention have also been disclosed.

Abstract: String matching a first string to a string stored in a string dictionary is performed by k-way hashing the first string and locating corresponding k hash locations in a first memory. When any of the k hash locations has a zero Bloom bit, the first string is deemed to not match any of the strings in the string dictionary. Otherwise, a sub-set of the k hash locations identified as those k hash locations having non-zero Bloom bits and a unique bit set to 1 each include a pointer that points to a string in the string dictionary that is fetched and compared to the first string wherein the fetches from the string dictionary are interleaved over the addresses from the first memory. A match signal is issued when the first string matches at least one of the strings stored in the dictionary.

Abstract: An efficient finite state machine implementation of a string matching that relies upon a Content Addressable Memory (CAM) or a CAM-equivalent collision-free hash-based lookup architecture with zero false positives used as a method for implementing large FSMs in hardware using a collision-free hash-based look up scheme with low average case bandwidth and power requirements that overcomes prior art limitations by providing the ability to match an anchored or unanchored input stream against a large dictionary of long and arbitrary length strings at line speed. It should be noted that in the context of the described embodiments, a string could take many forms, such as a set of characters, bits, numbers or any combination thereof.

Abstract: An efficient approach for SAT-based quantifier elimination and pre-image computation using unrolled designs that significantly improves the performance of pre-image and fix-point computation in SAT-based unbounded symbolic model checking.

Abstract: There is provided a method of solving a SAT problem comprising partitioning SAT-formula clauses in the SAT problem into a plurality of partitions. Each of said plurality of partitions is solved as a separate process each, thereby constituting a plurality of processes where each of said process communicates only with a subset of the plurality of processes.

Abstract: A system and method is disclosed for formal verification of software programs that advantageously bounds the ranges of values that a variable in the software can take during runtime.

Abstract: A method for optimizing voltage and frequency for pipelined architectures that offers better power efficiency. The invention provides methods for low-power high-throughput hardware implementations to stream computations by partitioning a computation into temporally distinct stages, assigning a clock frequency to each stage such that an overall computational throughput is met and assigning to each stage a supply voltage according to its respective clock frequency and circuit parameters.

Abstract: A computer-implemented method for augmenting SAT-based BMC to handle embedded memory designs without explicitly modeling memory bits. As is known, verifying designs having large embedded memories is typically handled by abstracting out (over-approximating) the memories. Such abstraction is not useful for finding real bugs. SAT-based BMC, as of now, is incapable of handling designs with explicit memory modeling due to enormously increased search space complexity. Advantageously, our method does not require analyzing the designs and also guarantees not to generate false negatives.

Abstract: A content-based information retrieval architecture is herein disclosed that can achieve correct and predictable high speed lookups while taking advantage of inexpensive conventional memory components. A content-based information retrieval architecture is herein disclosed that can achieve high speed lookups with a constant query time while taking advantage of inexpensive conventional memory components. In accordance with an embodiment of the invention, the architecture comprise a hashing module, a first table of encoded values, a second table of lookup values, and a third table of associated input values. The input value is hashed a number of times to generate a plurality of hashed values, the hashed values corresponding to locations of encoded values in the first table. The encoded values obtained from an input value encode an output value such that the output value cannot be recovered from any single encoded value.

Abstract: Simulation continues to be the primary technique for functional validation of designs. It is important that simulation vectors be effective in targeting the types of bugs designers expect to find rather than some generic coverage metrics. The focus of this work is to generate property-specific testbenches that are targeted either at proving the correctness of a property or at finding a bug. It is based on performing property-specific analysis on iteratively less abstract models of the design in order to obtain interesting paths in the form of a Witness Graph, which is then targeted during simulation of the entire design. This testbench generation framework will form an integral part of a comprehensive verification system currently being developed.

Abstract: An efficient approach for SAT-based quantifier elimination and pre-image computation using unrolled designs that significantly improves the performance of pre-image and fix-point computation in SAT-based unbounded symbolic model checking.

Abstract: A content-based information retrieval architecture is herein disclosed that can achieve correct and predictable high speed lookups while taking advantage of inexpensive conventional memory components.

Abstract: A system and method is disclosed for formal verification of software programs that advantageously translates the software, which can have bounded recursion, into a Boolean representation comprised of basic blocks and which applies SAT-based model checking to the Boolean representation.