Patents by Inventor Pranay Prabhat
Pranay Prabhat has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20240029811Abstract: Briefly, embodiments, such as methods and/or systems for operations and/or procedures to test magnetic memory devices. In a particular implementation, a bit error rate of a magnetic memory device may be estimated based, at least in part, on an observed bit error rate in the presence of an externally applied magnetic field.Type: ApplicationFiled: July 22, 2022Publication date: January 25, 2024Inventors: Pranay Prabhat, Mudit Bhargava, Fernando Garcia Redondo
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Patent number: 11841397Abstract: Subject matter disclosed herein may relate to wireless energy harvesting devices and may relate more particularly to system-on-a-chip testing for wireless energy harvesting devices.Type: GrantFiled: June 30, 2021Date of Patent: December 12, 2023Assignee: Arm LimitedInventors: Fernando Garcia Redondo, James Edward Myers, Parameshwarappa Anand Kumar Savanth, Pranay Prabhat, Gary Dale Carpenter
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Publication number: 20230317126Abstract: According to one implementation of the present disclosure, a circuit comprises: a memory array comprising one or more groupings of bitcells, one or more bitlines, and one or more wordlines; and one or more canary circuits coupled to the memory array, wherein each of the canary circuits is configured to predict at least partial breakdown of a corresponding grouping of bitcells in the memory array. According to one implementation of the present disclosure, a method includes: providing an excitation stress on one or more canary circuits corresponding to a grouping of bitcells in a memory array; detecting at least a partial breakdown of the one or more canary circuits; and generating a flag.Type: ApplicationFiled: March 30, 2022Publication date: October 5, 2023Inventors: Fernando GarcĂa Redondo, Pranay Prabhat, Mudit Bhargava, Supreet Jeloka
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Patent number: 11714564Abstract: According to one implementation of the present disclosure, a method for power management is disclosed. The method includes: computing, by a central processing unit, software instructions of a software workload in an active-mode operation corresponding to a first operating point on a performance curve of a performance mode; transitioning from instances of the active-mode operation to instances of standby-mode operation of the CPU, and recording, by a time tracking element, each of a plurality of standby entry data points; transitioning from the instances of the standby-mode operation to the instances of the active-mode operation of the CPU, and recording, by the time tracking element, each of a plurality of standby exit data points; and determining a second operating point on the performance curve of the performance mode based on the recorded standby entry data points and the recorded standby exit data points.Type: GrantFiled: January 6, 2020Date of Patent: August 1, 2023Assignee: Arm LimitedInventors: James Edward Myers, Pranay Prabhat, Matthew James Walker, Parameshwarappa Anand Kumar Savanth, Fernando Garcia Redondo
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Patent number: 11664681Abstract: Subject matter disclosed herein may relate to detecting wireless signals and/or signal packets and may relate more particularly to detecting wireless signals and/or signal packets at energy-harvesting devices.Type: GrantFiled: June 30, 2021Date of Patent: May 30, 2023Assignee: Arm LimitedInventors: Philex Ming-Yan Fan, Parameshwarappa Anand Kumar Savanth, Sahan Sajeewa Hiniduma Udugama Gamage, Pranay Prabhat, Benoit Labbe, Thanusree Achuthan
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Publication number: 20230003795Abstract: Subject matter disclosed herein may relate to wireless energy harvesting devices and may relate more particularly to system-on-a-chip testing for wireless energy harvesting devices.Type: ApplicationFiled: June 30, 2021Publication date: January 5, 2023Inventors: Fernando Garcia Redondo, James Edward Myers, Parameshwarappa Anand Kumar Savanth, Pranay Prabhat, Gary Dale Carpenter
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Publication number: 20230006467Abstract: Subject matter disclosed herein may relate to detecting wireless signals and/or signal packets and may relate more particularly to detecting wireless signals and/or signal packets at energy-harvesting devices.Type: ApplicationFiled: June 30, 2021Publication date: January 5, 2023Inventors: Philex Ming-Yan Fan, Parameshwarappa Anand Kumar Savanth, Sahan Sajeewa Hiniduma Udugama Gamage, Pranay Prabhat, Benoit Labbe, Thanusree Achuthan
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Patent number: 11521680Abstract: An integrated circuit includes a primary memory array with cells switchable between first and second states. The circuit also includes sacrificial memory cells; each fabricated to be switchable between the first and second states and associated with at least one row of the primary array. A controller is configured to detect a write operation to a row of the primary array, stress a sacrificial cell associated with the row and detect a failure of the associated sacrificial cell. The sacrificial cells are fabricated to have lower write-cycle endurance than cells of the primary array or are subjected to more stress. Failure of a row of the primary array is predicted based, at least in part, on a detected failure of the associated sacrificial cell.Type: GrantFiled: December 31, 2020Date of Patent: December 6, 2022Assignee: Arm LimitedInventors: Fernando Garcia Redondo, Mudit Bhargava, Pranay Prabhat, Supreet Jeloka
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Patent number: 11398813Abstract: Various implementations described herein refer to an integrated circuit having a first stage and a second stage. The first stage has a step-down converter coupled to an oscillator between a first voltage supply and a second voltage supply. The second stage is coupled to the first stage, and the second stage has a current bias generator coupled to a diode-connected transistor between the first voltage supply and the second voltage supply. The second stage provides an intermediate voltage to the first stage.Type: GrantFiled: January 25, 2021Date of Patent: July 26, 2022Assignee: Arm LimitedInventors: Philex Ming-Yan Fan, Parameshwarappa Anand Kumar Savanth, Benoit Labbe, Bal S. Sandhu, Pranay Prabhat, James Edward Myers
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Publication number: 20220208265Abstract: An integrated circuit includes a primary memory array with cells switchable between first and second states. The circuit also includes sacrificial memory cells; each fabricated to be switchable between the first and second states and associated with at least one row of the primary array. A controller is configured to detect a write operation to a row of the primary array, stress a sacrificial cell associated with the row and detect a failure of the associated sacrificial cell. The sacrificial cells are fabricated to have lower write-cycle endurance than cells of the primary array or are subjected to more stress. Failure of a row of the primary array is predicted based, at least in part, on a detected failure of the associated sacrificial cell.Type: ApplicationFiled: December 31, 2020Publication date: June 30, 2022Applicant: Arm LimitedInventors: Fernando Garcia Redondo, Mudit Bhargava, Pranay Prabhat, Supreet Jeloka
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Publication number: 20220172762Abstract: Various implementations described herein are related to a method. The method may apply a write control voltage to a bitcell. The method may gradually ramp the write control voltage to the bitcell. The method may terminate application of the write control voltage to the bitcell when a write operation is sensed in the bitcell.Type: ApplicationFiled: November 30, 2020Publication date: June 2, 2022Inventors: Supreet Jeloka, Mudit Bhargava, Pranay Prabhat, Femando Garcia Redondo
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Patent number: 11200940Abstract: According to one implementation of the present disclosure, a memory array to block read-access of uninitialized memory locations is disclosed. The memory array includes: a plurality of memory cells apportioned into a plurality of memory columns and a plurality of memory rows, where each of the memory cells is configured to store a single bit of memory data; and one or more initialization columns corresponding to at least one of the plurality of memory columns. The initialization state of a memory row of the memory cells may be configured to be stored in: the memory row; a latch of word-line driver circuitry coupled to the memory array; or a memory cell of the one or more initialization columns of a corresponding row of the plurality of memory rows of the memory array.Type: GrantFiled: November 13, 2019Date of Patent: December 14, 2021Assignee: Arm LimitedInventors: Pranay Prabhat, James Edward Myers, Graham Peter Knight
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Publication number: 20210208803Abstract: According to one implementation of the present disclosure, a method for power management is disclosed. The method includes: computing, by a central processing unit, software instructions of a software workload in an active-mode operation corresponding to a first operating point on a performance curve of a performance mode; transitioning from instances of the active-mode operation to instances of standby-mode operation of the CPU, and recording, by a time tracking element, each of a plurality of standby entry data points; transitioning from the instances of the standby-mode operation to the instances of the active-mode operation of the CPU, and recording, by the time tracking element, each of a plurality of standby exit data points; and determining a second operating point on the performance curve of the performance mode based on the recorded standby entry data points and the recorded standby exit data points.Type: ApplicationFiled: January 6, 2020Publication date: July 8, 2021Inventors: James Edward Myers, Pranay Prabhat, Matthew James Walker, Parameshwarappa Anand Kumar Savanth, Fernando Garcia Redondo
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Publication number: 20210142839Abstract: According to one implementation of the present disclosure, a memory array to block read-access of uninitialized memory locations is disclosed. The memory array includes: a plurality of memory cells apportioned into a plurality of memory columns and a plurality of memory rows, where each of the memory cells is configured to store a single bit of memory data; and one or more initialization columns corresponding to at least one of the plurality of memory columns. The initialization state of a memory row of the memory cells may be configured to be stored in: the memory row; a latch of word-line driver circuitry coupled to the memory array; or a memory cell of the one or more initialization columns of a corresponding row of the plurality of memory rows of the memory array.Type: ApplicationFiled: November 13, 2019Publication date: May 13, 2021Inventors: Pranay Prabhat, James Edward Myers, Graham Peter Knight
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Publication number: 20210143801Abstract: Various implementations described herein refer to an integrated circuit having a first stage and a second stage. The first stage has a step-down converter coupled to an oscillator between a first voltage supply and a second voltage supply. The second stage is coupled to the first stage, and the second stage has a current bias generator coupled to a diode-connected transistor between the first voltage supply and the second voltage supply. The second stage provides an intermediate voltage to the first stage.Type: ApplicationFiled: January 25, 2021Publication date: May 13, 2021Inventors: Philex Ming-Yan Fan, Parameshwarappa Anand Kumar Savanth, Benoit Labbe, Bal S. Sandhu, Pranay Prabhat, James Edward Myers
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Patent number: 10903822Abstract: Various implementations described herein refer to an integrated circuit having a first stage and a second stage. The first stage has a step-down converter coupled to an oscillator between a first voltage supply and a second voltage supply. The second stage is coupled to the first stage, and the second stage has a current bias generator coupled to a diode-connected transistor between the first voltage supply and the second voltage supply. The second stage provides an intermediate voltage to the first stage.Type: GrantFiled: March 5, 2019Date of Patent: January 26, 2021Assignee: Arm LimitedInventors: Philex Ming-Yan Fan, Parameshwarappa Anand Kumar Savanth, Benoit Labbe, Bal S. Sandhu, Pranay Prabhat, James Edward Myers
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Patent number: 10896707Abstract: Briefly, embodiments of claimed subject matter relate to adjusting, such as extending, a clock signal to permit completion of a write operations to a first memory type and/or to permit completion of read operations from a second memory type, wherein the first memory type and the second memory type are dissimilar from each other. In certain embodiments, the first memory type may comprise a magnetic random-access memory (MRAM) cell array, and the second memory type may comprise a static random-access memory (SRAM) cell array.Type: GrantFiled: March 1, 2019Date of Patent: January 19, 2021Assignee: Arm LimitedInventors: Andy Wangkun Chen, Rahul Mathur, Cyrille Nicolas Dray, Yann Sarrazin, Julien Vincent Poitrat, Yannis Jallamion-Grive, Pranay Prabhat, James Edward Myers, Graham Peter Knight, Jonas {hacek over (S)}vedas
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Publication number: 20200287524Abstract: Various implementations described herein refer to an integrated circuit having a first stage and a second stage. The first stage has a step-down converter coupled to an oscillator between a first voltage supply and a second voltage supply. The second stage is coupled to the first stage, and the second stage has a current bias generator coupled to a diode-connected transistor between the first voltage supply and the second voltage supply. The second stage provides an intermediate voltage to the first stage.Type: ApplicationFiled: March 5, 2019Publication date: September 10, 2020Inventors: Philex Ming-Yan Fan, Parameshwarappa Anand Kumar Savanth, Benoit Labbe, Bal S. Sandhu, Pranay Prabhat, James Edward Myers
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Patent number: 10726908Abstract: Various implementations described herein refer to an integrated circuit having a memory structure with an array of bitcells accessible via wordlines arranged in rows and bitlines arranged in columns. The integrated circuit may include source lines coupled to the bitcells. The integrated circuit may include source line drivers coupled between the wordlines and the source lines, and the source line drivers may allow the source lines to be used as switched source lines.Type: GrantFiled: August 21, 2018Date of Patent: July 28, 2020Assignee: Arm LimitedInventors: Supreet Jeloka, Pranay Prabhat, James Edward Myers
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Publication number: 20200194047Abstract: Briefly, embodiments of claimed subject matter relate to adjusting, such as extending, a clock signal to permit completion of a write operations to a first memory type and/or to permit completion of read operations from a second memory type, wherein the first memory type and the second memory type are dissimilar from each other. In certain embodiments, the first memory type may comprise a magnetic random-access memory (MRAM) cell array, and the second memory type may comprise a static random-access memory (SRAM) cell array.Type: ApplicationFiled: March 1, 2019Publication date: June 18, 2020Inventors: Andy Wangkun Chen, Rahul Mathur, Cyrille Nicolas Dray, Yann Sarrazin, Julien Vincent Poitrat, Yannis Jallamion-Grive, Pranay Prabhat, James Edward Myers, Graham Peter Knight, Jonas {hacek over (S)}vedas