Patents by Inventor Pranay Prabhat
Pranay Prabhat has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 10586790Abstract: Various implementations described herein are directed to an integrated circuit having a core array region with an array of memory devices. The integrated circuit may include a periphery region having periphery logic devices that interface with the array of memory devices. The integrated circuit may include a boundary region having one or more buffer devices coupled to body terminals of the periphery logic devices to drive the body terminals of the periphery logic devices using a body biasing signal provided by the one or more buffer devices.Type: GrantFiled: March 30, 2018Date of Patent: March 10, 2020Assignee: Arm LimitedInventors: Pranay Prabhat, James Edward Myers
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Publication number: 20200066358Abstract: Various implementations described herein refer to an integrated circuit having a memory structure with an array of bitcells accessible via wordlines arranged in rows and bitlines arranged in columns. The integrated circuit may include source lines coupled to the bitcells. The integrated circuit may include source line drivers coupled between the wordlines and the source lines, and the source line drivers may allow the source lines to be used as switched source lines.Type: ApplicationFiled: August 21, 2018Publication date: February 27, 2020Inventors: Supreet Jeloka, Pranay Prabhat, James Edward Myers
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Publication number: 20190304962Abstract: Various implementations described herein are directed to an integrated circuit having a core array region with an array of memory devices. The integrated circuit may include a periphery region having periphery logic devices that interface with the array of memory devices. The integrated circuit may include a boundary region having one or more buffer devices coupled to body terminals of the periphery logic devices to drive the body terminals of the periphery logic devices using a body biasing signal provided by the one or more buffer devices.Type: ApplicationFiled: March 30, 2018Publication date: October 3, 2019Inventors: Pranay Prabhat, James Edward Myers
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Patent number: 10411705Abstract: Area-efficient logic circuitry for checkpointing a register file using a mapper in an “in-order” CPU (central processing unit). A pair of flops with a shared master stage latch circuit implement storage elements in a register file and a checkpointed copy of the same register file.Type: GrantFiled: September 28, 2018Date of Patent: September 10, 2019Assignee: Arm LimitedInventors: Neil Burgess, Pranay Prabhat
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Patent number: 10354721Abstract: A storage bitcell comprising a first inverter cross-coupled with a second inverter, both the first and second inverter being in a path between a first potential and a second potential; wherein a first isolator is connected in the path between the first inverter and the first potential. The storage bitcell has particular application as Static Random-Access Memory (SRAM) circuitry.Type: GrantFiled: April 9, 2018Date of Patent: July 16, 2019Assignee: ARM LimitedInventors: Parameshwarappa Anand Kumar Savanth, James Edward Myers, Pranay Prabhat, David Walter Flynn, Shidhartha Das, David Michael Bull
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Patent number: 10181848Abstract: Embodiments are described for digital forward body biasing CMOS circuits. In an embodiment, a power management unit limits the amount of time for which digital forward body biasing may be implemented. In another embodiment, once a CMOS circuit is put into a full digital forward body bias mode, the CMOS circuit is gradually brought back to a zero forward body bias mode. In another embodiment, charge is shared among biased transistor wells during transition intervals when transitioning from one bias mode to another.Type: GrantFiled: January 27, 2017Date of Patent: January 15, 2019Assignee: ARM LimitedInventors: Pranay Prabhat, Parameshwarappa Anand Kumar Savanth, James Edward Myers
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Publication number: 20180233194Abstract: A storage bitcell comprising a first inverter cross-coupled with a second inverter, both the first and second inverter being in a path between a first potential and a second potential; wherein a first isolator is connected in the path between the first inverter and the first potential. The storage bitcell has particular application as Static Random-Access Memory (SRAM) circuitry.Type: ApplicationFiled: April 9, 2018Publication date: August 16, 2018Inventors: Parameshwarappa Anand Kumar Savanth, James Edward Myers, Pranay Prabhat, David Walter Flynn, Shidhartha Das, David Michael Bull
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Publication number: 20180219549Abstract: Embodiments are described for digital forward body biasing CMOS circuits. In an embodiment, a power management unit limits the amount of time for which digital forward body biasing may be implemented. In another embodiment, once a CMOS circuit is put into a full digital forward body bias mode, the CMOS circuit is gradually brought back to a zero forward body bias mode. In another embodiment, charge is shared among biased transistor wells during transition intervals when transitioning from one bias mode to another.Type: ApplicationFiled: January 27, 2017Publication date: August 2, 2018Inventors: Pranay Prabhat, Parameshwarappa Anand Kumar Savanth, James Edward Myers
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Patent number: 9940993Abstract: A storage bitcell comprising a first inverter cross-coupled with a second inverter, both the first and second inverter being in a path between a first potential and a second potential; wherein a first isolator is connected in the path between the first inverter and the first potential. The storage bitcell has particular application as Static Random-Access Memory (SRAM) circuitry.Type: GrantFiled: April 7, 2016Date of Patent: April 10, 2018Assignee: ARM LimitedInventors: Parameshwarappa Anand Kumar Savanth, James Edward Myers, Pranay Prabhat, David Walter Flynn, Shidhartha Das, David Michael Bull
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Patent number: 9911510Abstract: Various implementations described herein are directed to an integrated circuit having a memory cell array with multiple rows of memory cells including at least one redundant row of memory cells. The memory cell array may be partitioned into multiple regions of memory cells including a first region of memory cells corresponding to a first part of the redundant row of memory cells and a second region of memory cells corresponding to a second part of the redundant row of memory cells. The integrated circuit may include wordline driver circuitry coupled to the first and second regions of memory cells and their corresponding first and second parts of the redundant row of memory cells. In some instances, the integrated circuit may include row shift circuitry coupled to the first and second regions of memory cells and their corresponding first and second parts of the redundant row of memory cells.Type: GrantFiled: October 7, 2016Date of Patent: March 6, 2018Assignee: ARM LimitedInventors: Jungtae Kwon, Young Suk Kim, Vivek Nautiyal, Pranay Prabhat, Fakhruddin Ali Bohra, Shri Sagar Dwivedi, Satinderjit Singh, Lalit Gupta
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Publication number: 20170294222Abstract: A storage bitcell comprising a first inverter cross-coupled with a second inverter, both the first and second inverter being in a path between a first potential and a second potential; wherein a first isolator is connected in the path between the first inverter and the first potential. The storage bitcell has particular application as Static Random-Access Memory (SRAM) circuitry.Type: ApplicationFiled: April 7, 2016Publication date: October 12, 2017Inventors: Parameshwarappa Anand Kumar Savanth, James Edward Myers, Pranay Prabhat, David Walter Flynn, Shidhartha Das, David Michael Bull
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Patent number: 9786362Abstract: A memory circuit comprises an array of data storage elements; access circuitry to access a data bit, stored by a data storage element enabled for access, by an access signal for that data storage element; and control circuitry to enable groups of data storage elements for access, the groups having a group size, the group size being one or more, the access signals for data storage elements in a group being combined to provide a combined access signal common to that group of data storage elements; the control circuitry being configured to selectively operate in at least a first mode and a second mode, the group size in the first mode being different to the group size in the second mode.Type: GrantFiled: August 26, 2016Date of Patent: October 10, 2017Assignee: ARM LimitedInventors: Shidhartha Das, David Michael Bull, Pranay Prabhat, Adeline-Fleur Fleming
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Patent number: 9542994Abstract: A memory device and method of operating the memory device are provided. The memory device has bitcells arranged in a plurality of rows and columns. Row driver circuitry provides access to the array of bitcells by selection of an access row of the plurality of rows. The row driver circuitry comprises a retention control latch to store a retention control value and row power gating circuitry responsive to a retention signal to power gate at least one row when the retention control value has a first value and to leave the at least one row powered when the retention control value has a second value. Row-based retention of the content of the bit cells is thus provided, and the leakage current of the memory device when it is in a retention (e.g. sleep) mode, and only some of its rows contain valid data, can thus be reduced.Type: GrantFiled: September 15, 2015Date of Patent: January 10, 2017Assignee: ARM LimitedInventors: Pranay Prabhat, James Edward Myers
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Patent number: 8456939Abstract: Voltage regulation circuitry is provided comprising a pull-up p-type threshold device connecting a supply voltage node to an output voltage node, the pull-up p-type threshold device configured to be switched off in dependence on a control signal. A pull-down stack connects the output voltage node to a reference voltage node, the pull-down stack comprising a pull-down p-type threshold device and a pull-down n-type threshold device connected in series. An inverter is configured to receive an input from the output voltage node and is configured to generate a cut-off signal, wherein the pull-down n-type threshold device is configured to be switched on in dependence on the control signal and the pull-down p-type threshold device is configured to be switched off in dependence on the cut-off signal.Type: GrantFiled: November 22, 2010Date of Patent: June 4, 2013Assignee: ARM LimitedInventor: Pranay Prabhat
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Publication number: 20110141837Abstract: Voltage regulation circuitry is provided comprising a pull-up p-type threshold device connecting a supply voltage node to an output voltage node, the pull-up p-type threshold device configured to be switched off in dependence on a control signal. A pull-down stack connects the output voltage node to a reference voltage node, the pull-down stack comprising a pull-down p-type threshold device and a pull-down n-type threshold device connected in series. An inverter is configured to receive an input from the output voltage node and is configured to generate a cut-off signal, wherein the pull-down n-type threshold device is configured to be switched on in dependence on the control signal and the pull-down p-type threshold device is configured to be switched off in dependence on the cut-off signal.Type: ApplicationFiled: November 22, 2010Publication date: June 16, 2011Applicant: ARM LIMITEDInventor: Pranay Prabhat