Patents by Inventor Praneeth Akkinepally

Praneeth Akkinepally has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20210134727
    Abstract: An apparatus system is provided which comprises: a photoimageable dielectric layer; a first interconnect structure formed through the photoimageable dielectric, the first interconnect structure formed at least in part using a lithography process; and a second interconnect structure formed through the photoimageable dielectric, the second interconnect structure formed at least in part using a laser drilling process.
    Type: Application
    Filed: March 30, 2017
    Publication date: May 6, 2021
    Inventors: Robert A. May, Sri Ranga Sai BOYAPATI, Kristof DARMAWIKARTA, Hiroki TANAKA, Srinivas V. PIETAMBARAM, Frank TRUONG, Praneeth AKKINEPALLY, Andrew J. BROWN, Lauren A. LINK, Prithwish CHATTERJEE
  • Patent number: 10985080
    Abstract: An electronic package that includes a substrate and an electronic component attached to the substrate. A laminated layer is attached to an upper surface of the substrate such that the laminated layer covers the electronic component. The electronic package may further include a stiffener mounted on the laminated layer where the stiffener is over the electronic component.
    Type: Grant
    Filed: November 24, 2015
    Date of Patent: April 20, 2021
    Assignee: Intel Corporation
    Inventors: Pramod Malatkar, Kyle Yazzie, Naga Sivakumar Yagnamurthy, Richard J. Harries, Dilan Seneviratne, Praneeth Akkinepally, Xuefei Wan, Yonggang Li, Robert L. Sankman
  • Publication number: 20210098356
    Abstract: A substrate for an electronic device may include a first layer defining a first exterior surface of the substrate. The substrate may include a second layer defining a second exterior surface. The first layer and the second layer may include one or more sets of interconnects. The substrate may include one or more interconnect pockets, for instance in the second layer. Each of the interconnect pockets may be defined by a first pocket wall and a second pocket wall that may extend between the first pocket wall and the second exterior surface of the substrate. Individual ones of the second set of interconnects may be located within respective individual ones of the interconnect pockets in the second layer. The second pocket wall may extend from the first pocket wall at a wall angle that is greater than or equal to 90 degrees.
    Type: Application
    Filed: September 30, 2019
    Publication date: April 1, 2021
    Inventors: Praneeth Akkinepally, Jieying Kong, Frank Truong
  • Publication number: 20210090981
    Abstract: Embodiments of the present disclosure may generally relate to systems, apparatus, and/or processes directed to a manufacturing process flow for a pad that is substantially surrounded by a surface finish such as ENEPIG. Embodiments may be directed to a pad that has a first side and a second side opposite the first side, a VIA that has a first end and a second end, where the first end of the VIA is coupled with at least a portion of the first side of the pad, and a surface finish directly coupled with and surrounding a surface of the pad that excludes the at least the portion of the first side of the pad.
    Type: Application
    Filed: September 23, 2019
    Publication date: March 25, 2021
    Inventor: Praneeth AKKINEPALLY
  • Patent number: 10923443
    Abstract: A substrate for an electronic device may include a first layer, a second layer, and may include a third layer. The first layer may include a capacitive material, and the capacitive material may be segmented into a first section, and a second section. Each of the first section and the second section may include a first surface and a second surface. The second layer may include a first conductor. The third layer may include a second conductor. The first surface of the second section of capacitive material may be directly coupled to the first conductor. The second surface of the second section of the capacitive material may be directly coupled to the second conductor. A first filler region may include a dielectric material and the first filler region may be located in a first gap between the first section of capacitive material and the second section of capacitive material.
    Type: Grant
    Filed: March 29, 2019
    Date of Patent: February 16, 2021
    Assignee: Intel Corporation
    Inventors: Brandon C Marin, Shivasubramanian Balasubramanian, Rahul Jain, Praneeth Akkinepally, Jeremy D Ecton
  • Publication number: 20200312793
    Abstract: A substrate for an electronic device may include a first layer, a second layer, and may include a third layer. The first layer may include a capacitive material, and the capacitive material may be segmented into a first section, and a second section. Each of the first section and the second section may include a first surface and a second surface. The second layer may include a first conductor. The third layer may include a second conductor. The first surface of the second section of capacitive material may be directly coupled to the first conductor. The second surface of the second section of the capacitive material may be directly coupled to the second conductor. A first filler region may include a dielectric material and the first filler region may be located in a first gap between the first section of capacitive material and the second section of capacitive material.
    Type: Application
    Filed: March 29, 2019
    Publication date: October 1, 2020
    Inventors: Brandon C. Marin, Shivasubramanian Balasubramanian, Rahul Jain, Praneeth Akkinepally, Jeremy D. Ecton
  • Publication number: 20200144359
    Abstract: Disclosed embodiments include in-recess fabricated vertical capacitor cells, that can be assembled as close to the surface of a semiconductor package substrate as the first-level interconnect surface. The in-recess fabricated vertical capacitor cells are semiconductor package-integrated capacitors. Disclosed embodiments include laminated vertical capacitor cells where a plated through-hole is twice breached to form opposing capacitor plates. The breached, plated through-hole capacitors are semiconductor package-integrated capacitors.
    Type: Application
    Filed: January 8, 2020
    Publication date: May 7, 2020
    Inventors: Brandon C. Marin, Praneeth Akkinepally, Whitney Bryks, Dilan Seneviratne, Frank Truong
  • Patent number: 10546916
    Abstract: Disclosed embodiments include in-recess fabricated vertical capacitor cells, that can be assembled as close to the surface of a semiconductor package substrate as the first-level interconnect surface. The in-recess fabricated vertical capacitor cells are semiconductor package-integrated capacitors. Disclosed embodiments include laminated vertical capacitor cells where a plated through-hole is twice breached to form opposing capacitor plates. The breached, plated through-hole capacitors are semiconductor package-integrated capacitors.
    Type: Grant
    Filed: June 29, 2018
    Date of Patent: January 28, 2020
    Assignee: Intel Corporation
    Inventors: Brandon C Marin, Praneeth Akkinepally, Whitney Bryks, Dilan Seneviratne, Frank Truong
  • Publication number: 20200006468
    Abstract: Disclosed embodiments include in-recess fabricated vertical capacitor cells, that can be assembled as close to the surface of a semiconductor package substrate as the first-level interconnect surface. The in-recess fabricated vertical capacitor cells are semiconductor package-integrated capacitors. Disclosed embodiments include laminated vertical capacitor cells where a plated through-hole is twice breached to form opposing capacitor plates. The breached, plated through-hole capacitors are semiconductor package-integrated capacitors.
    Type: Application
    Filed: June 29, 2018
    Publication date: January 2, 2020
    Inventors: Brandon C. Marin, Praneeth Akkinepally, Whitney Bryks, Dilan Seneviratne, Frank Truong
  • Publication number: 20190389179
    Abstract: Embodiments are generally directed to dielectric film with pressure sensitive microcapsules of adhesion promoter. An embodiment of an apparatus includes a dielectric film, the dielectric film including a dielectric material layer; a layer of pressure sensitive microcapsules on a first side of the dielectric material layer, the microcapsules including an adhesion promoter; and a cover material on the layer of microcapsules. The pressure sensitive microcapsules are to rupture upon application of a certain rupture pressure.
    Type: Application
    Filed: March 17, 2017
    Publication date: December 26, 2019
    Inventors: Praneeth AKKINEPALLY, Frank TRUONG, Dilan SENEVIRATNE
  • Publication number: 20190333861
    Abstract: Described are microelectronic devices including an embedded die substrate including a molded component formed on or over a surface of a laminated substrate that provides a planar outer surface independent of the contour of the adjacent laminated substrate surface. The molded component may be formed over at least a portion of the embedded die. In other examples, the molded component and resulting planar outer surface may alternatively be on the backside of the substrate, away from the embedded die. The molded component may include an epoxy mold compound; and may be formed through processes including compression molding and transfer molding.
    Type: Application
    Filed: March 29, 2017
    Publication date: October 31, 2019
    Inventors: Srinivas V. Pietambaram, Rahul N. Manapalli, Praneeth Akkinepally, Jesse C. Jones, Yosuke Kanaoka, Dilan Seneviratne
  • Publication number: 20190287841
    Abstract: A system is disclosed, which comprises a component carrier having a first side, and a second side opposite the first side; and a light source to couple light into the carrier. In an example, the carrier is to propagate, through internal reflection, at least a portion the light to both the first and second sides of the carrier. The portion of light may be sufficient to release a first component and second component affixed to the first and second sides of the carrier via a first photosensitive layer and second photosensitive layer, respectively.
    Type: Application
    Filed: March 15, 2018
    Publication date: September 19, 2019
    Inventors: Frank Truong, Praneeth Akkinepally, Chelsea M. Groves, Whitney M. Bryks, Jason M. Gamba, Brandon C. Marin
  • Patent number: 10410940
    Abstract: An embodiment includes a method comprising: coupling a sacrificial material to a substrate; forming a first dielectric material adjacent the sacrificial material such that a horizontal axis intersects the first dielectric material and the sacrificial material; forming a first layer, on the first dielectric material and the sacrificial material, which includes a first metal interconnect and a third dielectric material; decoupling the substrate from the first dielectric material and the sacrificial material; removing the sacrificial material to form an empty cavity with sidewalls comprising the first dielectric material; after removing the sacrificial material to form the empty cavity, inserting a first die into the empty cavity; and forming a second dielectric material between the first dielectric material and the first die such that the horizontal axis intersects the first and second dielectric materials and the first die. Other embodiments are described herein.
    Type: Grant
    Filed: June 30, 2017
    Date of Patent: September 10, 2019
    Assignee: Intel Corporation
    Inventor: Praneeth Akkinepally
  • Publication number: 20190006252
    Abstract: An embodiment includes a method comprising: coupling a sacrificial material to a substrate; forming a first dielectric material adjacent the sacrificial material such that a horizontal axis intersects the first dielectric material and the sacrificial material; forming a first layer, on the first dielectric material and the sacrificial material, which includes a first metal interconnect and a third dielectric material; decoupling the substrate from the first dielectric material and the sacrificial material; removing the sacrificial material to form an empty cavity with sidewalls comprising the first dielectric material; after removing the sacrificial material to form the empty cavity, inserting a first die into the empty cavity; and forming a second dielectric material between the first dielectric material and the first die such that the horizontal axis intersects the first and second dielectric materials and the first die. Other embodiments are described herein.
    Type: Application
    Filed: June 30, 2017
    Publication date: January 3, 2019
    Inventor: Praneeth Akkinepally
  • Publication number: 20180350709
    Abstract: An electronic package that includes a substrate and an electronic component attached to the substrate. A laminated layer is attached to an upper surface of the substrate such that the laminated layer covers the electronic component. The electronic package may further include a stiffener mounted on the laminated layer where the stiffener is over the electronic component.
    Type: Application
    Filed: November 24, 2015
    Publication date: December 6, 2018
    Inventors: Pramod Malatkar, Kyle Yazzie, Naga Sivakumar Yagnamurthy, Richard J. Harries, Dilan Seneviratne, Praneeth Akkinepally, Xuefei Wan, Yonggang Li, Robert L. Sankman
  • Patent number: 10068776
    Abstract: An interlayer dielectric material includes a planar surface that exhibits planarity due to raster-patterned decomposition products due to use of a confocal light beam. The planar surface encompasses a filled via that is in electrical and physical contact with a bond pad that is also on the planar surface.
    Type: Grant
    Filed: June 29, 2017
    Date of Patent: September 4, 2018
    Assignee: Intel Corporation
    Inventors: Frank Truong, Praneeth Akkinepally, Shruti R. Jaywant, Dilan Seneviratne