Patents by Inventor Praneeth Akkinepally
Praneeth Akkinepally has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20230187331Abstract: Embodiments herein relate to systems, apparatuses, or processes directed to a package that includes a glass core with one or more openings with one or more dies placed in the opening such that the glass core surrounds the one or more dies. One or one or more through glass via filled with conductive material such as copper electrically couple a first side of the glass core with a second side of the glass core opposite the first side. Other embodiments may be described and/or claimed.Type: ApplicationFiled: December 13, 2021Publication date: June 15, 2023Inventors: Bainye Francoise ANGOUA, Chelsea GROVES, Frank TRUONG, Praneeth AKKINEPALLY, Whitney BRYKS
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Patent number: 11652071Abstract: A substrate for an electronic device may include a first layer, a second layer, and may include a third layer. The first layer may include a capacitive material, and the capacitive material may be segmented into a first section, and a second section. Each of the first section and the second section may include a first surface and a second surface. The second layer may include a first conductor. The third layer may include a second conductor. The first surface of the second section of capacitive material may be directly coupled to the first conductor. The second surface of the second section of the capacitive material may be directly coupled to the second conductor. A first filler region may include a dielectric material and the first filler region may be located in a first gap between the first section of capacitive material and the second section of capacitive material.Type: GrantFiled: January 26, 2021Date of Patent: May 16, 2023Assignee: Intel CorporationInventors: Brandon C Marin, Shivasubramanian Balasubramanian, Rahul Jain, Praneeth Akkinepally, Jeremy D Ecton
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Patent number: 11574874Abstract: An apparatus system is provided which comprises: a photoimageable dielectric layer; a first interconnect structure formed through the photoimageable dielectric, the first interconnect structure formed at least in part using a lithography process; and a second interconnect structure formed through the photoimageable dielectric, the second interconnect structure formed at least in part using a laser drilling process.Type: GrantFiled: March 30, 2017Date of Patent: February 7, 2023Assignee: Intel CorporationInventors: Robert A. May, Sri Ranga Sai Boyapati, Kristof Darmawikarta, Hiroki Tanaka, Srinivas V. Pietambaram, Frank Truong, Praneeth Akkinepally, Andrew J. Brown, Lauren A. Link, Prithwish Chatterjee
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Patent number: 11571876Abstract: Embodiments are generally directed to dielectric film with pressure sensitive microcapsules of adhesion promoter. An embodiment of an apparatus includes a dielectric film, the dielectric film including a dielectric material layer; a layer of pressure sensitive microcapsules on a first side of the dielectric material layer, the microcapsules including an adhesion promoter; and a cover material on the layer of microcapsules. The pressure sensitive microcapsules are to rupture upon application of a certain rupture pressure.Type: GrantFiled: March 17, 2017Date of Patent: February 7, 2023Assignee: Intel CorporationInventors: Praneeth Akkinepally, Frank Truong, Dilan Seneviratne
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Patent number: 11462432Abstract: A system is disclosed, which comprises a component carrier having a first side, and a second side opposite the first side; and a light source to couple light into the carrier. In an example, the carrier is to propagate, through internal reflection, at least a portion the light to both the first and second sides of the carrier. The portion of light may be sufficient to release a first component and second component affixed to the first and second sides of the carrier via a first photosensitive layer and second photosensitive layer, respectively.Type: GrantFiled: March 15, 2018Date of Patent: October 4, 2022Assignee: Intel CorporationInventors: Frank Truong, Praneeth Akkinepally, Chelsea M. Groves, Whitney M. Bryks, Jason M. Gamba, Brandon C. Marin
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Patent number: 11348865Abstract: A substrate for an electronic device may include one or more interconnect pockets. Each of the interconnect pockets may be defined by a first pocket wall and a second pocket wall that may extend between the first pocket wall and the second exterior surface of the substrate. The second pocket wall may extend from the first pocket wall at a wall angle that is greater than or equal to 90 degrees. Individual interconnects may be located within respective individual ones of the interconnect pockets.Type: GrantFiled: September 30, 2019Date of Patent: May 31, 2022Assignee: Intel CorporationInventors: Praneeth Akkinepally, Jieying Kong, Frank Truong
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Patent number: 11296186Abstract: Disclosed embodiments include in-recess fabricated vertical capacitor cells, that can be assembled as close to the surface of a semiconductor package substrate as the first-level interconnect surface. The in-recess fabricated vertical capacitor cells are semiconductor package-integrated capacitors. Disclosed embodiments include laminated vertical capacitor cells where a plated through-hole is twice breached to form opposing capacitor plates. The breached, plated through-hole capacitors are semiconductor package-integrated capacitors.Type: GrantFiled: January 8, 2020Date of Patent: April 5, 2022Assignee: Intel CorporationInventors: Brandon C Marin, Praneeth Akkinepally, Whitney Bryks, Dilan Seneviratne, Frank Truong
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Publication number: 20210366835Abstract: Microelectronic devices including an embedded die substrate including a molded component formed on or over a surface of a laminated substrate that provides a planar outer surface independent of the contour of the adjacent laminated. substrate surface. The molded component may be formed over at least a portion of the embedded die. In other examples, the molded component and resulting planar outer surface may alternatively be on the backside of the substrate, away from the embedded die. The molded component may include an epoxy mold compound; and may be formed through processes including compression molding and transfer molding.Type: ApplicationFiled: August 2, 2021Publication date: November 25, 2021Inventors: Srinivas Venkata Ramanuja Pietambaram, Rahul N. Manepalli, Praneeth Akkinepally, Jesse C. Jones, Yosuke Kanaoka, Dilan Seneviratne
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Patent number: 11081448Abstract: Microelectronic devices including an embedded die substrate including a molded component formed on or over a surface of a laminated substrate that, provides a planar outer surface independent of the contour of the adjacent laminated substrate surface. The molded component may be formed over at least a portion of the embedded die. In other examples, the molded component and resulting planar outer surface may alternatively be on the backside of the substrate, away from the embedded die. The molded component may include an epoxy mold compound; and may be formed through processes including compression molding and transfer molding.Type: GrantFiled: March 29, 2017Date of Patent: August 3, 2021Assignee: Intel CorporationInventors: Srinivas V. Pietambaram, Rahul N. Manepalli, Praneeth Akkinepally, Jesse C. Jones, Yosuke Kanaoka, Dilan Seneviratne
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Publication number: 20210151393Abstract: A substrate for an electronic device may include a first layer, a second layer, and may include a third layer. The first layer may include a capacitive material, and the capacitive material may be segmented into a first section, and a second section. Each of the first section and the second section may include a first surface and a second surface. The second layer may include a first conductor. The third layer may include a second conductor. The first surface of the second section of capacitive material may be directly coupled to the first conductor. The second surface of the second section of the capacitive material may be directly coupled to the second conductor. A first filler region may include a dielectric material and the first filler region may be located in a first gap between the first section of capacitive material and the second section of capacitive material.Type: ApplicationFiled: January 26, 2021Publication date: May 20, 2021Inventors: Brandon C Marin, Shivasubramanian Balasubramanian, Rahul Jain, Praneeth Akkinepally, Jeremy D Ecton
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Publication number: 20210134727Abstract: An apparatus system is provided which comprises: a photoimageable dielectric layer; a first interconnect structure formed through the photoimageable dielectric, the first interconnect structure formed at least in part using a lithography process; and a second interconnect structure formed through the photoimageable dielectric, the second interconnect structure formed at least in part using a laser drilling process.Type: ApplicationFiled: March 30, 2017Publication date: May 6, 2021Inventors: Robert A. May, Sri Ranga Sai BOYAPATI, Kristof DARMAWIKARTA, Hiroki TANAKA, Srinivas V. PIETAMBARAM, Frank TRUONG, Praneeth AKKINEPALLY, Andrew J. BROWN, Lauren A. LINK, Prithwish CHATTERJEE
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Patent number: 10985080Abstract: An electronic package that includes a substrate and an electronic component attached to the substrate. A laminated layer is attached to an upper surface of the substrate such that the laminated layer covers the electronic component. The electronic package may further include a stiffener mounted on the laminated layer where the stiffener is over the electronic component.Type: GrantFiled: November 24, 2015Date of Patent: April 20, 2021Assignee: Intel CorporationInventors: Pramod Malatkar, Kyle Yazzie, Naga Sivakumar Yagnamurthy, Richard J. Harries, Dilan Seneviratne, Praneeth Akkinepally, Xuefei Wan, Yonggang Li, Robert L. Sankman
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Publication number: 20210098356Abstract: A substrate for an electronic device may include a first layer defining a first exterior surface of the substrate. The substrate may include a second layer defining a second exterior surface. The first layer and the second layer may include one or more sets of interconnects. The substrate may include one or more interconnect pockets, for instance in the second layer. Each of the interconnect pockets may be defined by a first pocket wall and a second pocket wall that may extend between the first pocket wall and the second exterior surface of the substrate. Individual ones of the second set of interconnects may be located within respective individual ones of the interconnect pockets in the second layer. The second pocket wall may extend from the first pocket wall at a wall angle that is greater than or equal to 90 degrees.Type: ApplicationFiled: September 30, 2019Publication date: April 1, 2021Inventors: Praneeth Akkinepally, Jieying Kong, Frank Truong
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Publication number: 20210090981Abstract: Embodiments of the present disclosure may generally relate to systems, apparatus, and/or processes directed to a manufacturing process flow for a pad that is substantially surrounded by a surface finish such as ENEPIG. Embodiments may be directed to a pad that has a first side and a second side opposite the first side, a VIA that has a first end and a second end, where the first end of the VIA is coupled with at least a portion of the first side of the pad, and a surface finish directly coupled with and surrounding a surface of the pad that excludes the at least the portion of the first side of the pad.Type: ApplicationFiled: September 23, 2019Publication date: March 25, 2021Inventor: Praneeth AKKINEPALLY
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Patent number: 10923443Abstract: A substrate for an electronic device may include a first layer, a second layer, and may include a third layer. The first layer may include a capacitive material, and the capacitive material may be segmented into a first section, and a second section. Each of the first section and the second section may include a first surface and a second surface. The second layer may include a first conductor. The third layer may include a second conductor. The first surface of the second section of capacitive material may be directly coupled to the first conductor. The second surface of the second section of the capacitive material may be directly coupled to the second conductor. A first filler region may include a dielectric material and the first filler region may be located in a first gap between the first section of capacitive material and the second section of capacitive material.Type: GrantFiled: March 29, 2019Date of Patent: February 16, 2021Assignee: Intel CorporationInventors: Brandon C Marin, Shivasubramanian Balasubramanian, Rahul Jain, Praneeth Akkinepally, Jeremy D Ecton
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Publication number: 20200312793Abstract: A substrate for an electronic device may include a first layer, a second layer, and may include a third layer. The first layer may include a capacitive material, and the capacitive material may be segmented into a first section, and a second section. Each of the first section and the second section may include a first surface and a second surface. The second layer may include a first conductor. The third layer may include a second conductor. The first surface of the second section of capacitive material may be directly coupled to the first conductor. The second surface of the second section of the capacitive material may be directly coupled to the second conductor. A first filler region may include a dielectric material and the first filler region may be located in a first gap between the first section of capacitive material and the second section of capacitive material.Type: ApplicationFiled: March 29, 2019Publication date: October 1, 2020Inventors: Brandon C. Marin, Shivasubramanian Balasubramanian, Rahul Jain, Praneeth Akkinepally, Jeremy D. Ecton
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Publication number: 20200144359Abstract: Disclosed embodiments include in-recess fabricated vertical capacitor cells, that can be assembled as close to the surface of a semiconductor package substrate as the first-level interconnect surface. The in-recess fabricated vertical capacitor cells are semiconductor package-integrated capacitors. Disclosed embodiments include laminated vertical capacitor cells where a plated through-hole is twice breached to form opposing capacitor plates. The breached, plated through-hole capacitors are semiconductor package-integrated capacitors.Type: ApplicationFiled: January 8, 2020Publication date: May 7, 2020Inventors: Brandon C. Marin, Praneeth Akkinepally, Whitney Bryks, Dilan Seneviratne, Frank Truong
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Patent number: 10546916Abstract: Disclosed embodiments include in-recess fabricated vertical capacitor cells, that can be assembled as close to the surface of a semiconductor package substrate as the first-level interconnect surface. The in-recess fabricated vertical capacitor cells are semiconductor package-integrated capacitors. Disclosed embodiments include laminated vertical capacitor cells where a plated through-hole is twice breached to form opposing capacitor plates. The breached, plated through-hole capacitors are semiconductor package-integrated capacitors.Type: GrantFiled: June 29, 2018Date of Patent: January 28, 2020Assignee: Intel CorporationInventors: Brandon C Marin, Praneeth Akkinepally, Whitney Bryks, Dilan Seneviratne, Frank Truong
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Publication number: 20200006468Abstract: Disclosed embodiments include in-recess fabricated vertical capacitor cells, that can be assembled as close to the surface of a semiconductor package substrate as the first-level interconnect surface. The in-recess fabricated vertical capacitor cells are semiconductor package-integrated capacitors. Disclosed embodiments include laminated vertical capacitor cells where a plated through-hole is twice breached to form opposing capacitor plates. The breached, plated through-hole capacitors are semiconductor package-integrated capacitors.Type: ApplicationFiled: June 29, 2018Publication date: January 2, 2020Inventors: Brandon C. Marin, Praneeth Akkinepally, Whitney Bryks, Dilan Seneviratne, Frank Truong
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Publication number: 20190389179Abstract: Embodiments are generally directed to dielectric film with pressure sensitive microcapsules of adhesion promoter. An embodiment of an apparatus includes a dielectric film, the dielectric film including a dielectric material layer; a layer of pressure sensitive microcapsules on a first side of the dielectric material layer, the microcapsules including an adhesion promoter; and a cover material on the layer of microcapsules. The pressure sensitive microcapsules are to rupture upon application of a certain rupture pressure.Type: ApplicationFiled: March 17, 2017Publication date: December 26, 2019Inventors: Praneeth AKKINEPALLY, Frank TRUONG, Dilan SENEVIRATNE