Patents by Inventor Praneeth Akkinepally

Praneeth Akkinepally has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20190333861
    Abstract: Described are microelectronic devices including an embedded die substrate including a molded component formed on or over a surface of a laminated substrate that provides a planar outer surface independent of the contour of the adjacent laminated substrate surface. The molded component may be formed over at least a portion of the embedded die. In other examples, the molded component and resulting planar outer surface may alternatively be on the backside of the substrate, away from the embedded die. The molded component may include an epoxy mold compound; and may be formed through processes including compression molding and transfer molding.
    Type: Application
    Filed: March 29, 2017
    Publication date: October 31, 2019
    Inventors: Srinivas V. Pietambaram, Rahul N. Manapalli, Praneeth Akkinepally, Jesse C. Jones, Yosuke Kanaoka, Dilan Seneviratne
  • Publication number: 20190287841
    Abstract: A system is disclosed, which comprises a component carrier having a first side, and a second side opposite the first side; and a light source to couple light into the carrier. In an example, the carrier is to propagate, through internal reflection, at least a portion the light to both the first and second sides of the carrier. The portion of light may be sufficient to release a first component and second component affixed to the first and second sides of the carrier via a first photosensitive layer and second photosensitive layer, respectively.
    Type: Application
    Filed: March 15, 2018
    Publication date: September 19, 2019
    Inventors: Frank Truong, Praneeth Akkinepally, Chelsea M. Groves, Whitney M. Bryks, Jason M. Gamba, Brandon C. Marin
  • Patent number: 10410940
    Abstract: An embodiment includes a method comprising: coupling a sacrificial material to a substrate; forming a first dielectric material adjacent the sacrificial material such that a horizontal axis intersects the first dielectric material and the sacrificial material; forming a first layer, on the first dielectric material and the sacrificial material, which includes a first metal interconnect and a third dielectric material; decoupling the substrate from the first dielectric material and the sacrificial material; removing the sacrificial material to form an empty cavity with sidewalls comprising the first dielectric material; after removing the sacrificial material to form the empty cavity, inserting a first die into the empty cavity; and forming a second dielectric material between the first dielectric material and the first die such that the horizontal axis intersects the first and second dielectric materials and the first die. Other embodiments are described herein.
    Type: Grant
    Filed: June 30, 2017
    Date of Patent: September 10, 2019
    Assignee: Intel Corporation
    Inventor: Praneeth Akkinepally
  • Publication number: 20190006252
    Abstract: An embodiment includes a method comprising: coupling a sacrificial material to a substrate; forming a first dielectric material adjacent the sacrificial material such that a horizontal axis intersects the first dielectric material and the sacrificial material; forming a first layer, on the first dielectric material and the sacrificial material, which includes a first metal interconnect and a third dielectric material; decoupling the substrate from the first dielectric material and the sacrificial material; removing the sacrificial material to form an empty cavity with sidewalls comprising the first dielectric material; after removing the sacrificial material to form the empty cavity, inserting a first die into the empty cavity; and forming a second dielectric material between the first dielectric material and the first die such that the horizontal axis intersects the first and second dielectric materials and the first die. Other embodiments are described herein.
    Type: Application
    Filed: June 30, 2017
    Publication date: January 3, 2019
    Inventor: Praneeth Akkinepally
  • Publication number: 20180350709
    Abstract: An electronic package that includes a substrate and an electronic component attached to the substrate. A laminated layer is attached to an upper surface of the substrate such that the laminated layer covers the electronic component. The electronic package may further include a stiffener mounted on the laminated layer where the stiffener is over the electronic component.
    Type: Application
    Filed: November 24, 2015
    Publication date: December 6, 2018
    Inventors: Pramod Malatkar, Kyle Yazzie, Naga Sivakumar Yagnamurthy, Richard J. Harries, Dilan Seneviratne, Praneeth Akkinepally, Xuefei Wan, Yonggang Li, Robert L. Sankman
  • Patent number: 10068776
    Abstract: An interlayer dielectric material includes a planar surface that exhibits planarity due to raster-patterned decomposition products due to use of a confocal light beam. The planar surface encompasses a filled via that is in electrical and physical contact with a bond pad that is also on the planar surface.
    Type: Grant
    Filed: June 29, 2017
    Date of Patent: September 4, 2018
    Assignee: Intel Corporation
    Inventors: Frank Truong, Praneeth Akkinepally, Shruti R. Jaywant, Dilan Seneviratne