Abstract: Transistor devices including stressors are disclosed. One such transistor device includes a channel region, a dielectric layer and a semiconductor substrate. The channel region is configured to provide a conductive channel between a source region and a drain region. In addition, the dielectric layer is below the channel region and is configured to electrically insulate the channel region. Further, the semiconductor substrate, which is below the channel region and below the dielectric layer, includes dislocation defects at a top surface of the semiconductor substrate, where the dislocation defects are collectively oriented to impose a compressive strain on the channel region such that charge carrier mobility is enhanced in the channel region.

Abstract: Multigate transistor devices and methods of their fabrication are disclosed. In accordance with one method, a fin and a gate structure that is disposed on a plurality of surfaces of the fin are formed. In addition, at least a portion of an extension of the fin is removed to form a recessed portion that is below the gate structure, is below a channel region of the fin, and includes at least one angled indentation. Further, a terminal extension is grown in the at least one angled indentation below the channel region and along a surface of the channel region such that the terminal extension provides a stress on the channel region to enhance charge carrier mobility in the channel region.

Abstract: In one exemplary embodiment of the invention, a method includes: providing an inversion mode varactor having a substrate, a backgate layer overlying the substrate, an insulating layer overlying the backgate layer, a semiconductor layer overlying the insulating layer and at least one metal-oxide semiconductor field effect transistor (MOSFET) device disposed upon the semiconductor layer, where the semiconductor layer includes a source region and a drain region, where the at least one MOSFET device includes a gate stack defining a channel between the source region and the drain region, where the gate stack has a gate dielectric layer overlying the semiconductor layer and a conductive layer overlying the gate dielectric layer; and applying a bias voltage to the backgate layer to form an inversion region in the semiconductor layer at an interface between the semiconductor layer and the insulating layer.

Abstract: An integrated circuit includes an SOI substrate with a unitary N+ layer below the BOX, a P region in the N+ layer, an eDRAM with an N+ plate, and logic/SRAM devices above the P region. The P region functions as a back gate of the logic/SRAM devices. An optional intrinsic (undoped) layer can be formed between the P back gate layer and the N+ layer to reduce the junction field and lower the junction leakage between the P back gate and the N+ layer. In another embodiment an N or N+ back gate can be formed in the P region. The N+ back gate functions as a second back gate of the logic/SRAM devices. The N+ plate of the SOI eDRAM, the P back gate, and the N+ back gate can be electrically biased at the same or different voltage potentials. Methods to fabricate the integrated circuits are also disclosed.

Abstract: Carbon-doped semiconductor material portions are formed on a subset of surfaces of underlying semiconductor surfaces contiguously connected to a channel of a field effect transistor. Carbon-doped semiconductor material portions can be formed by selective epitaxy of a carbon-containing semiconductor material layer or by shallow implantation of carbon atoms into surface portions of the underlying semiconductor surfaces. The carbon-doped semiconductor material portions can be deposited as layers and subsequently patterned by etching, or can be formed after formation of disposable masking spacers. Raised source and drain regions are formed on the carbon-doped semiconductor material portions and on physically exposed surfaces of the underlying semiconductor surfaces.

Abstract: A method of creating a semiconductor integrated circuit is disclosed. The method includes forming a first field effect transistor (FET) device and a second FET device on a semiconductor substrate. The method includes epitaxially growing raised source/drain (RSD) structures for the first FET device at a first height. The method includes epitaxially growing raised source/drain (RSD) structures for the second FET device at a second height. The second height is greater than the first height such that a threshold voltage of the second FET device is greater than a threshold voltage of the first FET device.

Abstract: A transistor, for example a FinFET, includes a gate structure disposed over a substrate. The gate structure has a width and also a length and a height defining two opposing sidewalls of the gate structure. The transistor further includes at least one electrically conductive channel between a source region and a drain region that passes through the sidewalls of the gate structure; a dielectric layer disposed over the gate structure and portions of the electrically conductive channel that are external to the gate structure; and an air gap underlying the dielectric layer. The air gap is disposed adjacent to the sidewalls of the gate structure and functions to reduce parasitic capacitance of the transistor. At least one method to fabricate the transistor is also disclosed.

Abstract: Methods are disclosed to fabricate a transistor, for example a FinFET, by forming over a substrate at least one electrically conductive channel between a source region and a drain region; forming a gate structure to be disposed over a portion of the channel, the gate structure having a width and a length and a height defining two opposing sidewalls of the gate structure and being formed such that the channel said passes through the sidewalls; forming spacers on the sidewalls; forming a layer of epitaxial silicon over the channel; removing the spacers; and forming a dielectric layer to be disposed over the gate structure and portions of the channel that are external to the gate structure such that a capacitance-reducing air gap underlies the dielectric layer and is disposed adjacent to the sidewalls of said gate structure in a region formerly occupied by the spacers.

Abstract: A method of forming a semiconductor structure which includes an extremely thin silicon-on-insulator (ETSOI) semiconductor structure having a PFET portion and an NFET portion, a gate structure in the PFET portion and the NFET portion, a high quality nitride spacer adjacent to the gate structures in the PFET portion and the NFET portion and a doped faceted epitaxial silicon germanium raised source/drain (RSD) in the PFET portion. An amorphous silicon layer is formed on the RSD in the PFET portion. A faceted epitaxial silicon RSD is formed on the ETSOI adjacent to the high quality nitride in the NFET portion. The amorphous layer in the PFET portion prevents epitaxial growth in the PFET portion during formation of the RSD in the NFET portion. Extensions are ion implanted into the ETSOI underneath the gate structure in the NFET portion.

Abstract: A method is provided for fabricating a transistor. According to the method, a second semiconductor layer is formed on a first semiconductor layer, and a dummy gate structure is formed on the second semiconductor layer. A gate spacer is formed on sidewalls of the dummy gate structure, and the dummy gate structure is removed to form a cavity. The second semiconductor layer beneath the cavity is removed. A gate dielectric is formed on the first portion of the first semiconductor layer and adjacent to the sidewalls of the second semiconductor layer and sidewalls of the gate spacer. A gate conductor is formed on the first portion of the gate dielectric and abutting the second portion of the gate dielectric. Raised source/drain regions are formed in the second semiconductor layer, with at least part of the raised source/drain regions being below the gate spacer.

Abstract: MOSFETs and methods for making MOSFETs with a recessed channel and abrupt junctions are disclosed. The method includes creating source and drain extensions while a dummy gate is in place. The source/drain extensions create a diffuse junction with the silicon substrate. The method continues by removing the dummy gate and etching a recess in the silicon substrate. The recess intersects at least a portion of the source and drain junction. Then a channel is formed by growing a silicon film to at least partially fill the recess. The channel has sharp junctions with the source and drains, while the unetched silicon remaining below the channel has diffuse junctions with the source and drain. Thus, a MOSFET with two junction regions, sharp and diffuse, in the same transistor can be created.

Abstract: The present disclosure, which is directed to ultra-thin-body-and-BOX and Double BOX fully depleted SOI devices having an epitaxial diffusion-retarding semiconductor layer that slows dopant diffusion into the SOI channel, and a method of making these devices. Dopant concentrations in the SOI channels of the devices of the present disclosure having an epitaxial diffusion-retarding semiconductor layer between the substrate and SOI channel are approximately 50 times less than the dopant concentrations measured in SOI channels of devices without the epitaxial diffusion-retarding semiconductor layer.

Abstract: A semiconductor device is provided that includes a gate structure present on a substrate. The gate structure includes a gate conductor with an undercut region in sidewalls of a first portion of the gate conductor, wherein a second portion of the gate conductor is present over the first portion of the gate conductor and includes a protruding portion over the undercut region. A spacer is adjacent to sidewalls of the gate structure, wherein the spacer includes an extending portion filling the undercut region. A raised source region and a raised drain region is present adjacent to the spacers. The raised source region and the raised drain region are separated from the gate conductor by the extending portion of the spacers.

Abstract: Shallow trench isolation structures are provided for use with UTBB (ultra-thin body and buried oxide) semiconductor substrates, which prevent defect mechanisms from occurring, such as the formation of electrical shorts between exposed portions of silicon layers on the sidewalls of shallow trench of a UTBB substrate, in instances when trench fill material of the shallow trench is subsequently etched away and recessed below an upper surface of the UTBB substrate.

Abstract: Shallow trench isolation structures are provided for use with UTBB (ultra-thin body and buried oxide) semiconductor substrates, which prevent defect mechanisms from occurring, such as the formation of electrical shorts between exposed portions of silicon layers on the sidewalls of shallow trench of a UTBB substrate, in instances when trench fill material of the shallow trench is subsequently etched away and recessed below an upper surface of the UTBB substrate.

Abstract: A method of forming a transistor device includes forming a patterned gate structure over a semiconductor substrate, forming a raised source region over the semiconductor substrate adjacent a source side of the gate structure, and forming silicide contacts on the raised source region, on the patterned gate structure, and on the semiconductor substrate adjacent a drain side of the gate structure. Thereby, a hybrid field effect transistor (FET) structure having a drain side Schottky contact and a raised source side ohmic contact is defined.

Abstract: A semiconductor structure which includes a semiconductor on insulator (SOI) substrate. The SOI substrate includes a base semiconductor layer; a buried oxide (BOX) layer in contact with the base semiconductor layer; and an SOI layer in contact with the BOX layer. The semiconductor structure further includes a circuit formed with respect to the SOI layer, the circuit including an N type field effect transistor (NFET) having source and drain extensions in the SOI layer and a gate; and a P type field effect transistor (PFET) having source and drain extensions in the SOI layer and a gate. There may also be a well under each of the NFET and PFET. There is a nonzero electrical bias being applied to the SOI substrate. One of the NFET extensions and PFET extensions may be underlapped with respect to the NFET gate or PFET gate, respectively.

Abstract: An electrical circuit, planar diode, and method of forming a diode and one or more CMOS devices on the same chip. The method includes electrically isolating a portion of a substrate in a diode region from other substrate regions. The method also includes recessing the substrate in the diode region. The method further includes epitaxially forming in the diode region a first doped layer above the substrate and epitaxially forming in the diode region a second doped layer above the first doped layer.

Abstract: A method for forming an electrical device that includes forming a high-k gate dielectric layer over a semiconductor substrate that is patterned to separate a first portion of the high-k gate dielectric layer that is present on a first conductivity device region from a second portion of the high-k gate dielectric layer that is present on a second conductivity device region. A connecting gate conductor is formed on the first portion and the second portion of the high-k gate dielectric layer. The connecting gate conductor extends from the first conductivity device region over the isolation region to the second conductivity device region. One of the first conductivity device region and the second conductivity device region may then be exposed to an oxygen containing atmosphere. Exposure with the oxygen containing atmosphere modifies a threshold voltage of the semiconductor device that is exposed.

Abstract: A method of forming a field effect transistor (FET) device includes forming a patterned gate structure over a substrate; forming a solid source dopant material on the substrate, adjacent sidewall spacers of the gate structure; performing an anneal process at a temperature sufficient to cause dopants from the solid source dopant material to diffuse within the substrate beneath the gate structure and form source/drain extension regions; following formation of the source/drain extension regions, forming trenches in the substrate adjacent the sidewall spacers, corresponding to source/drain regions; and forming an embedded semiconductor material in the trenches so as to provide a stress on a channel region of the substrate defined beneath the gate structure.