Patents by Inventor Prasad Chalasani

Prasad Chalasani has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240185304
    Abstract: A digital ad-buying platform uses counterfactual-based incrementality measurement by implementing randomization and/or a correction for auction win bias to avoid the need to identify counterfactual winner types in the control group. This approach can estimate impact at the individual consumer level. Confidence levels can be determined using Gibbs sampling in the context of causal analysis in the presence of non-compliance.
    Type: Application
    Filed: December 14, 2022
    Publication date: June 6, 2024
    Inventors: Prasad Chalasani, Ari Buchalter, Ezra Winston, Jaynth Thiagarajan
  • Patent number: 11556964
    Abstract: A digital ad-buying platform uses counterfactual-based incrementality measurement by implementing randomization and/or a correction for auction win bias to avoid the need to identify counterfactual winner types in the control group. This approach can estimate impact at the individual consumer level. Confidence levels can be determined using Gibbs sampling in the context of causal analysis in the presence of non-compliance.
    Type: Grant
    Filed: September 27, 2021
    Date of Patent: January 17, 2023
    Assignee: MediaMath, Inc.
    Inventors: Prasad Chalasani, Ari Buchalter, Ezra Winston, Jaynth Thiagarajan
  • Publication number: 20220084075
    Abstract: A digital ad-buying platform uses counterfactual-based incrementality measurement by implementing randomization and/or a correction for auction win bias to avoid the need to identify counterfactual winner types in the control group. This approach can estimate impact at the individual consumer level. Confidence levels can be determined using Gibbs sampling in the context of causal analysis in the presence of non-compliance.
    Type: Application
    Filed: September 27, 2021
    Publication date: March 17, 2022
    Inventors: Prasad Chalasani, Ari Buchalter, Ezra Winston, Jaynth Thiagarajan
  • Publication number: 20210357988
    Abstract: A digital ad-buying platform uses counterfactual-based incrementality measurement by implementing randomization and/or a correction for auction win bias to avoid the need to identify counterfactual winner types in the control group. This approach can estimate impact at the individual consumer level. Confidence levels can be determined using Gibbs sampling in the context of causal analysis in the presence of non-compliance.
    Type: Application
    Filed: March 1, 2021
    Publication date: November 18, 2021
    Inventors: Prasad Chalasani, Ari Buchalter, Ezra Winston, Jaynth Thiagarajan
  • Patent number: 11170413
    Abstract: A digital ad-buying platform uses counterfactual-based incrementality measurement by implementing randomization and/or a correction for auction win bias to avoid the need to identify counterfactual winner types in the control group. This approach can estimate impact at the individual consumer level. Confidence levels can be determined using Gibbs sampling in the context of causal analysis in the presence of non-compliance.
    Type: Grant
    Filed: March 1, 2021
    Date of Patent: November 9, 2021
    Assignee: MediaMath, Inc.
    Inventors: Prasad Chalasani, Ari Buchalter, Ezra Winston, Jaynth Thiagarajan
  • Patent number: 11144937
    Abstract: A marketplace diagnostics framework for analyzing and managing online marketplaces.
    Type: Grant
    Filed: July 26, 2018
    Date of Patent: October 12, 2021
    Assignee: VERIZON MEDIA INC.
    Inventors: Tarun Bhatia, Prasad Chalasani, Rohit Chandra
  • Patent number: 10977697
    Abstract: A digital ad-buying platform uses counterfactual-based incrementality measurement by implementing randomization and/or a correction for auction win bias to avoid the need to identify counterfactual winner types in the control group. This approach can estimate impact at the individual consumer level. Confidence levels can be determined using Gibbs sampling in the context of causal analysis in the presence of non-compliance.
    Type: Grant
    Filed: May 29, 2019
    Date of Patent: April 13, 2021
    Assignee: MediaMath, Inc.
    Inventors: Prasad Chalasani, Ari Buchalter, Ezra Winston, Jaynth Thiagarajan
  • Publication number: 20210077957
    Abstract: Disclosed herein are membranes, composition for forming membranes, methods for forming membranes, and sensors and other devices comprising membranes. The membrane comprises a polyurethane component, the polyurethane component comprising a blend of from 5 wt % to 95 wt %, based on the total weight of the polyurethane component, of an amphiphilic polyurethane, and from 5 wt % to 95 wt %, based on the total weight of the polyurethane component, of a hydrophobic polyurethane.
    Type: Application
    Filed: August 28, 2018
    Publication date: March 18, 2021
    Inventors: Jennifer AL-RASHID, Chad SUGIYAMA, John ZUPANCICH, Durga Prasad CHALASANI
  • Patent number: 10922548
    Abstract: Systems, methods, and non-transitory computer-readable media can receive a set of video frames associated with a video. A determination can be made that a threshold number of video frames of the set of video frames depict two or more reaction icons of a set of reaction icons. The video can be identified as a poll video based on the determining that the threshold number of video frames of the set of video frames depict two or more reaction icons of the set of reaction icons.
    Type: Grant
    Filed: December 27, 2018
    Date of Patent: February 16, 2021
    Assignee: Facebook, Inc.
    Inventors: Lei Huang, Jianyu Wang, Guangshuo Liu, Renbin Peng, Ziheng Wang, Raghu Prasad Chalasani
  • Patent number: 10791203
    Abstract: A multi-protocol receiver for receiving at least one input signal comprises: a comparator, a protection controller, and a multi-stage current mode logic (“CML”) buffer. The comparator compares a reference voltage and a predefined voltage. At least one output of the comparator is coupled to at least one input of the protection controller. The multi-stage current mode logic buffer receives the input signal and the reference voltage. Outputs of the protection controller are coupled to control inputs of the multi-stage CML buffer for operating the multi-stage CML buffer to process the input signal and the reference signal.
    Type: Grant
    Filed: October 26, 2017
    Date of Patent: September 29, 2020
    Assignee: Synopsys, Inc.
    Inventors: Prasad Chalasani, Venkata N. S. N. Rao, Majid Jalali Far
  • Patent number: 10505550
    Abstract: A synchronizing high-speed clock divider has a Clk input, a Clks input, and a reset input configured to correct phase misalignment on clock divider outputs caused by phase skew between a Clk input signal and a Clks input signal, and comprises a reset synchronizer configured to generate at least one synchronous internal reset signal in response to a reset signal and the Clk input signal, a first clock divider configured to receive the Clk input signal on the Clk input and a reset signal on a first clock divider reset input to provide a Clk out signal, a second clock divider configured to receive the Clks input signal on the Clks input and the reset signal on a second clock divider reset input to provide a Clks out signal, a phase skew detector configured to detect a phase alignment between the Clk out signal and the Clks out signal, and a phase skew corrector coupled to the phase skew detector and the second clock divider configured to change the phase alignment to be within a same phase as the first clock div
    Type: Grant
    Filed: February 5, 2019
    Date of Patent: December 10, 2019
    Assignee: Invecas, Inc.
    Inventors: Shaolei Quan, Vijay Gadde, Prasad Chalasani
  • Patent number: 10502769
    Abstract: A digital voltmeter, where a number of clock pulses for a first ramp voltage to reach an input voltage is determined. Next, a number of clock pulses for a second ramp voltage to reach the input voltage is determined. One of the first and the second ramp voltages having a least number of clock pulses to reach the input voltage is determined. A determination is made for a number of clock pulses for the determined one of the first and the second ramp voltages to reach a reference voltage. A digital code is generated for the input voltage based on the determined number of clock pulses for reaching the reference voltage and the determined least number of clock pulses for reaching the input voltage.
    Type: Grant
    Filed: September 7, 2017
    Date of Patent: December 10, 2019
    Inventors: William Loh, Venkata N. S. N. Rao, Prasad Chalasani
  • Publication number: 20190347697
    Abstract: A digital ad-buying platform uses counterfactual-based incrementality measurement by implementing randomization and/or a correction for auction win bias to avoid the need to identify counterfactual winner types in the control group. This approach can estimate impact at the individual consumer level. Confidence levels can be determined using Gibbs sampling in the context of causal analysis in the presence of non-compliance.
    Type: Application
    Filed: May 29, 2019
    Publication date: November 14, 2019
    Inventors: Prasad Chalasani, Ari Buchalter, Ezra Winston, Jaynth Thiagarajan
  • Patent number: 10467659
    Abstract: A digital ad-buying platform uses counterfactual-based incrementality measurement by implementing randomization and/or a correction for auction win bias to avoid the need to identify counterfactual winner types in the control group. This approach can estimate impact at the individual consumer level. Confidence levels can be determined using Gibbs sampling in the context of causal analysis in the presence of non-compliance.
    Type: Grant
    Filed: August 2, 2017
    Date of Patent: November 5, 2019
    Assignee: MediaMath, Inc.
    Inventors: Prasad Chalasani, Ari Buchalter, Ezra Winston, Jaynth Thiagarajan
  • Patent number: 10361684
    Abstract: A pulse-width-to-voltage (“PWV”) converter, comprises: a switch, a capacitor, a current source, and a current sink. The switch is operable by a signal. The current source, the current sink, and the switch are serially connected across a high voltage potential and a low voltage potential. An output node is coupled to a serial connection between the current source and the current sink. An end of the capacitor is coupled to the output node for converting a current into a control voltage indicative of a duty cycle of the signal.
    Type: Grant
    Filed: July 19, 2017
    Date of Patent: July 23, 2019
    Assignee: Invecas, Inc.
    Inventors: Venkata N. S. N. Rao, Majid Jalali Far, Prasad Chalasani, Aram Martirosyan
  • Publication number: 20190132428
    Abstract: A multi-protocol receiver for receiving at least one input signal comprises: a comparator, a protection controller, and a multi-stage current mode logic (“CML”) buffer. The comparator compares a reference voltage and a predefined voltage. At least one output of the comparator is coupled to at least one input of the protection controller. The multi-stage current mode logic buffer receives the input signal and the reference voltage. Outputs of the protection controller are coupled to control inputs of the multi-stage CML buffer for operating the multi-stage CML buffer to process the input signal and the reference signal.
    Type: Application
    Filed: October 26, 2017
    Publication date: May 2, 2019
    Inventors: Prasad Chalasani, Venkata N.S.N. Rao, Majid Jalali Far
  • Publication number: 20190072589
    Abstract: A digital voltmeter, where a number of clock pulses for a first ramp voltage to reach an input voltage is determined. Next, a number of clock pulses for a second ramp voltage to reach the input voltage is determined. One of the first and the second ramp voltages having a least number of clock pulses to reach the input voltage is determined. A determination is made for a number of clock pulses for the determined one of the first and the second ramp voltages to reach a reference voltage. A digital code is generated for the input voltage based on the determined number of clock pulses for reaching the reference voltage and the determined least number of clock pulses for reaching the input voltage.
    Type: Application
    Filed: September 7, 2017
    Publication date: March 7, 2019
    Inventors: William Loh, Venkata N.S.N. Rao, Prasad Chalasani
  • Publication number: 20190028090
    Abstract: A pulse-width-to-voltage (“PWV”) converter, comprises: a switch, a capacitor, a current source, and a current sink. The switch is operable by a signal. The current source, the current sink, and the switch are serially connected across a high voltage potential and a low voltage potential. An output node is coupled to a serial connection between the current source and the current sink. An end of the capacitor is coupled to the output node for converting a current into a control voltage indicative of a duty cycle of the signal.
    Type: Application
    Filed: July 19, 2017
    Publication date: January 24, 2019
    Inventors: Venkata N.S.N. Rao, Majid Jalali Far, Prasad Chalasani, Aram Martirosyan
  • Publication number: 20180336581
    Abstract: A marketplace diagnostics framework for analyzing and managing online marketplaces.
    Type: Application
    Filed: July 26, 2018
    Publication date: November 22, 2018
    Inventors: Tarun BHATIA, Prasad CHALASANI, Rohit CHANDRA
  • Patent number: 10094859
    Abstract: A power voltage detector comprises voltage sensors for sensing supply voltages; and a logic. The logic combines the sensed supply voltages to generate a logic output indicative of whether the sensed supply voltages have met one or more predefined thresholds. Each of the voltage sensors has diode-connected transistors and passive resistance. The diode-connected transistors and the passive resistance are serially connected for generating an output, where the output is coupled to an input of the logic.
    Type: Grant
    Filed: July 19, 2017
    Date of Patent: October 9, 2018
    Assignee: Invecas, Inc.
    Inventors: Venkata N. S. N. Rao, Prasad Chalasani, Majid Jalali Far