Patents by Inventor Prasanth Perugupalli
Prasanth Perugupalli has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11947099Abstract: Aspects of present disclosure relate to real-time image generation. An exemplary apparatus for real time image generation includes at least an optical system, a slide port configured to hold a slide, an actuator mechanism mechanically connected to a mobile element, a user interface comprising an input interface and an output interface, at least processor configured to: using the at least an optical system, capture a first image of the slide at a first position, modify the first image, using the output interface, display the first image to a user, using the input interface, receive a parameter set from the user.Type: GrantFiled: July 25, 2023Date of Patent: April 2, 2024Inventors: Ganesh Ramamoorthy, Prasanth Perugupalli
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Publication number: 20240028831Abstract: As apparatus for detecting associations among datasets of different types is disclosed. The apparatus includes at least a processor and a memory communicatively connected to the at least a processor. The memory instructs the processor to receive a plurality of datasets from a user. The memory instructs the processor to identify a first set of associations between the plurality of datasets. The memory instructs the processor to generate a second set of associations as a function of the first set of associations using a second association classifier. Generating a second set of associations includes training the second association classifier using a using second association training data, wherein second association training data comprises a plurality of data entries containing the first set of associations as inputs correlated to the second set of associations as outputs The memory instructs the processor to display the second set of associations using a display device.Type: ApplicationFiled: June 30, 2023Publication date: January 25, 2024Applicant: Pramana Inc.Inventors: Jaya JAIN, Prasanth PERUGUPALLI, Rakesh BARVE
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Patent number: 9636064Abstract: A system and a method for monitoring subject's eyes are disclosed. In one embodiment, spectral profiles of a frame substantially around a subject's eye are received from an image capturing device. Further, a state of the subject's eye in the frame is detected using the spectral profiles received from the image capturing device.Type: GrantFiled: September 19, 2015Date of Patent: May 2, 2017Assignees: IMEC India Private Limited, IMEC VZWInventors: Prasanth Perugupalli, Sumit Kumar Nath
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Publication number: 20160106355Abstract: A system and a method for monitoring subject's eyes are disclosed. In one embodiment, spectral profiles of a frame substantially around a subject's eye are received from an image capturing device. Further, a state of the subject's eye in the frame is detected using the spectral profiles received from the image capturing device.Type: ApplicationFiled: September 19, 2015Publication date: April 21, 2016Applicants: IMEC VZW, IMEC INDIA PRIVATE LIMITEDInventors: Prasanth Perugupalli, Sumit Kumar Nath
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Publication number: 20140036767Abstract: The present application discloses various implementations of a wireless docking system. In one implementation, such a wireless docking system includes a docking surface and at least one wireless transceiver configured to establish a wireless connection with a portable device. The wireless connection results in interoperability of the portable device and another device connected to the wireless docking system.Type: ApplicationFiled: October 10, 2012Publication date: February 6, 2014Applicant: BROADCOM CORPORATIONInventors: Prasanth Perugupalli, Brima Ibrahim
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Patent number: 7728671Abstract: An RF power circuit comprises a power transistor having a gate and drain, an output matching network coupled to the drain and an input matching network coupled to the gate. A closed-loop bias circuit is integrated with the power transistor on the same die and coupled to the gate for biasing the RF power transistor based on a reference voltage applied to the bias circuit.Type: GrantFiled: January 17, 2008Date of Patent: June 1, 2010Assignee: Infineon Technologies AGInventors: Cynthia Blair, Prasanth Perugupalli
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Publication number: 20090184756Abstract: An RF power circuit comprises a power transistor having a gate and drain, an output matching network coupled to the drain and an input matching network coupled to the gate. A closed-loop bias circuit is integrated with the power transistor on the same die and coupled to the gate for biasing the RF power transistor based on a reference voltage applied to the bias circuit.Type: ApplicationFiled: January 17, 2008Publication date: July 23, 2009Applicant: INFINEON TECHNOLOGIES NORTH AMERICA CORP.Inventors: Cynthia Blair, Prasanth Perugupalli
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Patent number: 7564303Abstract: A semiconductor power device comprises a flange, a die having a gate, a source, and a drain. The source is electrically coupled to the flange. A drain matching circuit is located on the flange having an input, an output and a bias input, the input being coupled with the drain. The drain matching circuit comprises an inductor coupled in series with a first capacitor between the drain and flange and a second capacitor arranged next to the first capacitor, wherein the second capacitor is coupled with the bias input and in parallel with the first capacitor through a second inductor. An input terminal is mechanically coupled to the flange and electrically coupled with the gate, an output terminal is mechanically coupled to the flange and electrically coupled with the output of the drain matching circuit, and an input bias terminal is mechanically coupled to the flange and electrically coupled with the drain through the bias input.Type: GrantFiled: July 26, 2005Date of Patent: July 21, 2009Assignee: Infineon Technologies AGInventors: Prasanth Perugupalli, Stan Lopuch, Nagaraj V. Dixit
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Publication number: 20080231373Abstract: One embodiment of the invention provides an output circuit for a transistor. The output circuit includes a first capacitor coupled between ground and a drain electrode of the transistor via a first bond wire and a second bond wire coupling which couples a node between said first bond wire coupling and said first capacitor with ground via a second capacitor.Type: ApplicationFiled: March 20, 2007Publication date: September 25, 2008Inventors: Hafizur Rahman, Prasanth Perugupalli, Nagaraj Dixit
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Publication number: 20070024358Abstract: A semiconductor power device comprises a flange, a die having a gate, a source, and a drain. The source is electrically coupled to the flange. A drain matching circuit is located on the flange having an input, an output and a bias input, the input being coupled with the drain. The drain matching circuit comprises an inductor coupled in series with a first capacitor between the drain and flange and a second capacitor arranged next to the first capacitor, wherein the second capacitor is coupled with the bias input and in parallel with the first capacitor through a second inductor. An input terminal is mechanically coupled to the flange and electrically coupled with the gate, an output terminal is mechanically coupled to the flange and electrically coupled with the output of the drain matching circuit, and an input bias terminal is mechanically coupled to the flange and electrically coupled with the drain through the bias input.Type: ApplicationFiled: July 26, 2005Publication date: February 1, 2007Inventors: Prasanth Perugupalli, Stan Lopuch, Nagaraj Dixit
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Patent number: 6806106Abstract: A method for manufacturing a power transistor circuit includes securing a die to a substrate, the die comprising a transistor having an input terminal and an output terminal. One or more performance characteristics of the transistor are measured. Using one or more wire sets, the transistor input terminal is electrically connected to one or more input matching elements and an input signal lead. The impedance of the one or more wire sets, as determined by selecting a desired number and/or length of the wires in each set, is selected based at least in part on the measured transistor performance characteristic(s). Similarly, using one or more additional wire sets, the transistor output terminal is electrically connected to one or more output matching elements and an output signal lead, wherein the impedance of the additional wire sets is selected based at least in part on the measured transistor performance characteristic(s).Type: GrantFiled: March 20, 2001Date of Patent: October 19, 2004Assignee: Infineon Technologies AGInventors: Larry Leighton, Prasanth Perugupalli, Nagaraj Dixit, Tom Moller
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Patent number: 6734728Abstract: Conventional broadband RF power amplifiers use a ¼ wavelength transmission line to decouple the gate bias DC source from the gate circuitry and a second ¼ wavelength transmission line to decouple the drain bias DC source from the drain circuitry, taking up considerable printed circuit board space. A novel broadband RF power amplifier uses a transistor with separate terminals for injection of gate bias and drain bias DC sources, eliminating the need for ¼ wavelength transmission lines, thereby freeing up space and allowing higher density packaging. The power amplifier transistor can be implemented with a single die circuit or multiple die circuits operating in parallel.Type: GrantFiled: December 19, 2002Date of Patent: May 11, 2004Assignee: Infineon Technologies North America Corp.Inventors: Larry Leighton, Prasanth Perugupalli, Nagaraj V. Dixit, Gordon C. Ma
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Patent number: 6614308Abstract: A broadband RF signal amplifier includes a plurality of transistors attached to a surface of a pedestal, each transistor having an input and an output. An RF input path electrically connected to the transistor inputs includes a passive splitter implemented in a multi-layer printed circuit board and configured to split a RF input signal into a plurality of component input signals. A plurality of corresponding input matching networks including one-quarter wavelength transmission lines implemented in the printed circuit board couple respective component input signals to the transistor inputs at an input impedance, the input matching networks further comprising respective input matching capacitors attached to the pedestal. An RF output path electrically connected to the transistor outputs includes a passive combiner implemented in the printed circuit board and configured to combine component output signals received at the transistor outputs into a RF output signal.Type: GrantFiled: October 22, 2001Date of Patent: September 2, 2003Assignee: Infineon Technologies AGInventors: Thomas W. Moller, Larry Leighton, Prasanth Perugupalli
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Patent number: 6583673Abstract: A multistage power amplifier circuit with superior isolation between gain stages provides alternative common lead currents paths from the individual gain stage elements to obtain improved stability and operational performance.Type: GrantFiled: February 26, 2001Date of Patent: June 24, 2003Assignee: Infineon Technologies AGInventors: Bengt Ahl, Prasanth Perugupalli, Larry Leighton
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Publication number: 20030076173Abstract: A broadband RF signal amplifier includes a plurality of transistors attached to a surface of a pedestal, each transistor having an input and an output. An RF input path electrically connected to the transistor inputs includes a passive splitter implemented in a multi-layer printed circuit board and configured to split a RF input signal into a plurality of component input signals. A plurality of corresponding input matching networks including one-quarter wavelength transmission lines implemented in the printed circuit board couple respective component input signals to the transistor inputs at an input impedance, the input matching networks further comprising respective input matching capacitors attached to the pedestal. An RF output path electrically connected to the transistor outputs includes a passive combiner implemented in the printed circuit board and configured to combine component output signals received at the transistor outputs into a RF output signal.Type: ApplicationFiled: October 22, 2001Publication date: April 24, 2003Applicant: Telefonaktiebolaget LM EricssonInventors: Thomas W. Moller, Larry Leighton, Prasanth Perugupalli
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Patent number: 6466094Abstract: Gain and bandwidth enhancement of a RF power amplifier package is effected by electrically coupling a power transistor to a RF signal source with an inductance, and further electrically coupling the input and common element terminals of the power transistor with a shunt inductance. The shunt inductance is chosen such that its reactance is the conjugate of the reactance of the power transistor's common-input capacitance. A similar conjugate matching output circuit is provided to electrically couple the transistor's output and common element terminals to a load. The shunt inductors are implemented on the package substrate by connecting the respective input and output transistor terminals to grounded shunt caps via bond wires.Type: GrantFiled: January 10, 2001Date of Patent: October 15, 2002Assignee: Ericsson Inc.Inventors: Larry C. Leighton, Prasanth Perugupalli
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Publication number: 20020145184Abstract: A push-pull transistor chip comprises a single a semiconductor die having first and second LDMOS transistors formed thereon and configured for push-pull operation, the first and second transistors sharing a common element current region. In a power transistor package, the push-pull transistor chip is attached to a mounting flange serving as a common element ground reference, wherein a conductor (e.g., one or more bond wires) electrically connects the shared common element current region to the mounting flange.Type: ApplicationFiled: April 5, 2001Publication date: October 10, 2002Applicant: Ericsson Inc.Inventors: Prasanth Perugupalli, Larry Leighton
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Publication number: 20020134993Abstract: A method for manufacturing a power transistor circuit includes securing a die to a substrate, the die comprising a transistor having an input terminal and an output terminal. One or more performance characteristics of the transistor are measured. Using one or more wire sets, the transistor input terminal is electrically connected to one or more input matching elements and an input signal lead. The impedance of the one or more wire sets, (as determined by selecting a desired number and/or length of the wires in each set, is selected based at least in part on the measured transistor performance characteristic(s). Similarly, using one or more additional wire sets, the transistor output terminal is electrically connected to one or more output matching elements and an output signal lead, wherein the impedance of the additional wire sets is selected based at least in part on the measured transistor performance characteristic(s).Type: ApplicationFiled: March 20, 2001Publication date: September 26, 2002Applicant: Ericsson Inc.Inventors: Larry Leighton, Prasanth Perugupalli, Nagaraj V. Dixit, Tom Moller
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Patent number: 6455905Abstract: A push-pull transistor chip comprises a single/semiconductor die having first and second LDMOS transistors formed thereon and configured for push-pull operation, the first and second transistors sharing a common element current region. In a power transistor package, the push-pull transistor chip is attached to a mounting flange serving as a common element ground reference, wherein a conductor (e.g., one or more bond wires) electrically connects the shared common element current region to the mounting flange.Type: GrantFiled: April 5, 2001Date of Patent: September 24, 2002Assignee: Ericsson Inc.Inventors: Prasanth Perugupalli, Larry Leighton
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Publication number: 20020125955Abstract: Gain and bandwidth enhancement of a RF power amplifier package is effected by electrically coupling a power transistor to a RF signal source with an inductance, and further electrically coupling the input and common element terminals of the power transistor with a shunt inductance. The shunt inductance is chosen such that its reactance is the conjugate of the reactance of the power transistor's common-input capacitance. A similar conjugate matching output circuit is provided to electrically couple the transistor's output and common element terminals to a load. The shunt inductors are implemented on the package substrate by connecting the respective input and output transistor terminals to grounded shunt caps via bond wires.Type: ApplicationFiled: January 10, 2001Publication date: September 12, 2002Applicant: Ericsson Inc.Inventors: Larry C. Leighton, Prasanth Perugupalli