Abstract: A push-pull transistor chip comprises a single a semiconductor die having first and second LDMOS transistors formed thereon and configured for push-pull operation, the first and second transistors sharing a common element current region. In a power transistor package, the push-pull transistor chip is attached to a mounting flange serving as a common element ground reference, wherein a conductor (e.g., one or more bond wires) electrically connects the shared common element current region to the mounting flange.

Abstract: A method for manufacturing a power transistor circuit includes securing a die to a substrate, the die comprising a transistor having an input terminal and an output terminal. One or more performance characteristics of the transistor are measured. Using one or more wire sets, the transistor input terminal is electrically connected to one or more input matching elements and an input signal lead. The impedance of the one or more wire sets, (as determined by selecting a desired number and/or length of the wires in each set, is selected based at least in part on the measured transistor performance characteristic(s). Similarly, using one or more additional wire sets, the transistor output terminal is electrically connected to one or more output matching elements and an output signal lead, wherein the impedance of the additional wire sets is selected based at least in part on the measured transistor performance characteristic(s).

Abstract: A push-pull transistor chip comprises a single/semiconductor die having first and second LDMOS transistors formed thereon and configured for push-pull operation, the first and second transistors sharing a common element current region. In a power transistor package, the push-pull transistor chip is attached to a mounting flange serving as a common element ground reference, wherein a conductor (e.g., one or more bond wires) electrically connects the shared common element current region to the mounting flange.

Abstract: Gain and bandwidth enhancement of a RF power amplifier package is effected by electrically coupling a power transistor to a RF signal source with an inductance, and further electrically coupling the input and common element terminals of the power transistor with a shunt inductance. The shunt inductance is chosen such that its reactance is the conjugate of the reactance of the power transistor's common-input capacitance. A similar conjugate matching output circuit is provided to electrically couple the transistor's output and common element terminals to a load. The shunt inductors are implemented on the package substrate by connecting the respective input and output transistor terminals to grounded shunt caps via bond wires.

Abstract: A power transistor according to one embodiment of the invention includes a plurality of transistor elements located on a single semiconductor die, each transistor element comprising one or more transistors coupled to a common gate terminal for the respective transistor element. A resistor network couples the transistor element gate terminals between a bias voltage and a reference ground, with resistors in the network sized such that such that a first transistor element is biased in a first, e.g., class A, operating condition, and a second transistor element is biased in a second, e.g., class AB operating condition.

Abstract: A multistage power amplifier circuit with superior isolation between gain stages provides alternative common lead currents paths from the individual gain stage elements to obtain improved stability and operational performance.