Patents by Inventor Prasenjit Bhowmik
Prasenjit Bhowmik has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20220407567Abstract: A system for a radio access network (RAN) includes a radio unit (RU) configured to receive first in-phase and quadrature (I/Q) data represented in a first domain from a distributed unit (DU). The system includes a beamformer associated with the RU. The beamformer is configured to receive the first I/Q data represented in the first domain. The beamformer is also configured to transmit second I/Q data represented in the first domain based on the first I/Q data in the first domain. The system also includes a transceiver associated with the RU. The transceiver is configured to receive the second I/Q data represented in the first domain. The transceiver is also configured to convert the second I/Q data represented in the first domain to second I/Q data represented in a second domain.Type: ApplicationFiled: June 19, 2022Publication date: December 22, 2022Inventors: Sameer Madhav GANDHI, Praveen Ghanashyam SHEKOKAR, Subramanian Anantharaman CHANDRASEKARAPURAM, Prasenjit BHOWMIK
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Publication number: 20200021250Abstract: Systems and methods are provided for clocking scheme to reduce nonlinear distortion. An example system may include at least two processing paths, each including at least one circuit exhibiting nonlinear behavior. Nonlinearity may be managed during processing of signals, such as by assessing effects of the nonlinear behavior during the processing of signals, and controlling clocking applied via at least one path based on the assessed effects, to reduce the effects of the nonlinear behavior during the processing of signals, eliminating the need for post-processing corrections. The controlling of clocking may include adjusting timing of a clock applied in the at least path, such as by introducing a timing-delay adjustment to a clock when the clock is applied to a circuit after the circuit exhibiting nonlinear behavior. A timing-advancement may be applied to signals processed via the at least one path, particularly before the circuit exhibiting nonlinear behavior.Type: ApplicationFiled: September 26, 2019Publication date: January 16, 2020Inventors: Prasun Kali Bhattacharyya, Abhishek Ghosh, Prasenjit Bhowmik
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Publication number: 20190341892Abstract: A transconductance circuit comprises a first transistor, a second transistor, a first source-degeneration device, a second source-degeneration device, a first feedback device, and a second feedback device. The gate node of the first transistor is coupled to a source node of the second transistor via the first feedback device. The gate node of the second transistor is coupled to a source node of the second transistor via the second feedback device. The source node of the first transistor is coupled to a reference voltage via the first source-degeneration device. The source node of the second transistor is coupled to the reference voltage via the second source-degeneration device.Type: ApplicationFiled: May 1, 2019Publication date: November 7, 2019Inventors: Anand Mohan Pappu, Ranjit Kumar Guntreddi, Madhusudan Govindarajan, Pranjal Pandey, Prasenjit Bhowmik
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Patent number: 10187017Abstract: Systems and methods are provided for clocking scheme to reduce nonlinear distortion. An example system may comprise at least two processing paths, each comprising at least one circuit exhibiting nonlinear behavior. Nonlinearity may be managed during processing of signals, such as by assessing effects of the nonlinear behavior during the processing of signals, and controlling clocking applied via at least one path based on the assessed effects, to reduce the effects of the nonlinear behavior during the processing of signals, eliminating the need for post-processing corrections. The controlling of clocking may comprise adjusting timing of a clock applied in the at least path, such as by introducing a timing-delay adjustment to a clock when the clock is applied to a circuit after the circuit exhibiting nonlinear behavior. A timing-advancement may be applied to signals processed via the at least one path, particularly before the circuit exhibiting nonlinear behavior.Type: GrantFiled: April 4, 2017Date of Patent: January 22, 2019Assignee: MAXLINEAR, INC.Inventors: Prasun Kali Bhattacharyya, Abhishek Ghosh, Prasenjit Bhowmik
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Publication number: 20180198419Abstract: Systems and methods are provided for clocking scheme to reduce nonlinear distortion. An example system may comprise at least two processing paths, each comprising at least one circuit exhibiting nonlinear behavior. Nonlinearity may be managed during processing of signals, such as by assessing effects of the nonlinear behavior during the processing of signals, and controlling clocking applied via at least one path based on the assessed effects, to reduce the effects of the nonlinear behavior during the processing of signals, eliminating the need for post-processing corrections. The controlling of clocking may comprise adjusting timing of a clock applied in the at least path, such as by introducing a timing-delay adjustment to a clock when the clock is applied to a circuit after the circuit exhibiting nonlinear behavior. A timing-advancement may be applied to signals processed via the at least one path, particularly before the circuit exhibiting nonlinear behavior.Type: ApplicationFiled: April 4, 2017Publication date: July 12, 2018Inventors: Prasun Kali Bhattacharyya, Abhishek Ghosh, Prasenjit Bhowmik
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Publication number: 20170346396Abstract: A switching regulator circuit includes a gate driver circuit driving a first switch and a second switch to generate a first voltage at a first node. Further, the switching regulator includes an LC filter circuit responsive to the first voltage to generate a desired output voltage. Moreover, the switching regulator includes a regulator circuit coupled to the LC filter circuit to control the gate driver circuit. The regulator circuit accurately controls variations in trip point. The trip point is a voltage at which the second switch is switched OFF by the gate control circuit. The regulator circuit includes one of a Delay Locked Loop (DLL) and a Pulse width modulator (PWM) controller.Type: ApplicationFiled: August 16, 2017Publication date: November 30, 2017Applicant: Cirel Systems Private LimitedInventors: Leela Madhav Lakkimsetti, Raghavendra Rao Haresamudram, Prasenjit Bhowmik
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Patent number: 9762121Abstract: A switching regulator circuit includes a gate driver circuit driving a first switch and a second switch to generate a first voltage at a first node. Further, the switching regulator includes an LC filter circuit responsive to the first voltage to generate a desired output voltage. Moreover, the switching regulator includes a regulator circuit coupled to the LC filter circuit to control the gate driver circuit. The regulator circuit accurately controls variations in trip point. The trip point is a voltage at which the second switch is switched OFF by the gate control circuit. The regulator circuit includes one of a Delay Locked Loop (DLL) and a Pulse width modulator (PWM) controller.Type: GrantFiled: August 11, 2014Date of Patent: September 12, 2017Assignee: Cirel Systems Private LimitedInventors: Leela Madhav Lakkimsetti, Raghavendra Rao Haresamudram, Prasenjit Bhowmik
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Publication number: 20160344398Abstract: Systems and methods are provided for cascaded phase-locked loops (PLLs). A plurality of phase-locked loops (PLLs) arranged in a cascaded manner may be used in providing enhanced signal generation. Each PLL generates an output based on a corresponding input and a feedback signal. The input to a first one of plurality of cascaded phase-locked loops (PLLs) comprises an input reference signal; the input to each remaining one of the plurality of the cascaded phase-locked loops (PLLs) corresponds to an output of a preceding one of the plurality of the cascaded phase-locked loops (PLLs); and the output of a last one of the plurality of cascaded phase-locked loops (PLLs) corresponds to an overall output signal of the plurality of cascaded phase-locked loops (PLLs). The frequency of the overall output signal is set based on the one or more adjustments applied in each one of the plurality of cascaded phase-locked loops (PLLs).Type: ApplicationFiled: May 20, 2016Publication date: November 24, 2016Inventors: Prasun Kali Bhattacharyya, Prasenjit Bhowmik, Vamsi Paidi
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Publication number: 20150333611Abstract: A switching regulator circuit includes a gate driver circuit driving a first switch and a second switch to generate a first voltage at a first node. Further, the switching regulator includes an LC filter circuit responsive to the first voltage to generate a desired output voltage. Moreover, the switching regulator includes a regulator circuit coupled to the LC filter circuit to control the gate driver circuit. The regulator circuit accurately controls variations in trip point. The trip point is a voltage at which the second switch is switched OFF by the gate control circuit. The regulator circuit includes one of a Delay Locked Loop (DLL) and a Pulse width modulator (PWM) controller.Type: ApplicationFiled: August 11, 2014Publication date: November 19, 2015Inventors: Leela Madhav Lakkimsetti, Raghavendra Rao Haresamudram, Prasenjit Bhowmik
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Publication number: 20150042386Abstract: A power-on reset (POR) circuit for generating a POR signal includes a current source to generate an input current. The input current is a supply voltage dependent current. The POR circuit includes a first diode operable to receive the input current to output a first voltage signal. The first diode is electrically connected in series with a resistor. Further, the POR circuit includes a second diode operable to receive the input current to output a second voltage signal. Further, the POR circuit includes a comparator operable to receive the first voltage signal and the second voltage signal to generate the POR signal at a predefined trip point. The predefined trip point is a point at which the first voltage signal equals the second voltage signal. Furthermore, the POR circuit includes a temperature compensation circuit to compensate for the variation of the predefined trip point.Type: ApplicationFiled: December 24, 2013Publication date: February 12, 2015Applicant: CIREL SYSTEMS PRIVATE LIMITEDInventors: PRASENJIT BHOWMIK, PRANJAL PANDEY
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Publication number: 20140145768Abstract: The main feedback loop of a PLL/DLL receives a reference clock and an output clock as inputs, and operates to achieve one or both of a phase and a frequency lock of the output clock with respect to the reference clock. The PLL/DLL includes an RS-latch connected to receive the output clock and the reference clock. The RS-Latch generates a digital output representing a phase difference between the reference clock and the output clock. A correction block in the PLL/DLL receives the digital output and adjusts an electrical characteristic of the main feedback loop by a value that is based on a polarity of the digital output. Effects of offset-errors in the PLL/DLL are thereby minimized or corrected for.Type: ApplicationFiled: February 8, 2013Publication date: May 29, 2014Applicant: COSMIC CIRCUITS PVT LTDInventors: Rishi Mathur, Jyoti Arya, Prasenjit Bhowmik
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Patent number: 8723566Abstract: The main feedback loop of a PLL/DLL receives a reference clock and an output clock as inputs, and operates to achieve one or both of a phase and a frequency lock of the output clock with respect to the reference clock. The PLL/DLL includes an RS-latch connected to receive the output clock and the reference clock. The RS-Latch generates a digital output representing a phase difference between the reference clock and the output clock. A correction block in the PLL/DLL receives the digital output and adjusts an electrical characteristic of the main feedback loop by a value that is based on a polarity of the digital output. Effects of offset-errors in the PLL/DLL are thereby minimized or corrected for.Type: GrantFiled: February 8, 2013Date of Patent: May 13, 2014Assignee: Cadence AMS Design India Private LimitedInventors: Rishi Mathur, Jyoti Arya, Prasenjit Bhowmik
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Patent number: 8659362Abstract: A relaxation oscillator circuit with reduced sensitivity of oscillation frequency to comparator delay variation includes a first current source that generates charging current, a second current source coupled to the first current source to generate reference voltage, a resistor coupled to the second current source to enable generation of the reference voltage, a capacitor coupled to the first current source that is charged based on the charging current, a comparator responsive to voltage corresponding to the capacitor and the reference voltage to generate output voltage, a peak detector coupled to the capacitor to generate peak voltage, an error detector coupled to the peak detector and the second current source to generate an error based on the peak voltage and the reference voltage, and a controller coupled to the error detector to control one of the charging current, offset voltage input to the comparator, and capacitance of the capacitor.Type: GrantFiled: November 22, 2011Date of Patent: February 25, 2014Assignee: Cadence AMS Design India Private LimitedInventors: Prasenjit Bhowmik, Rishi Mathur, Sriram Ganesan, Sunil Rajan
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Publication number: 20120319789Abstract: A relaxation oscillator circuit with reduced sensitivity of oscillation frequency to comparator delay variation includes a first current source that generates charging current, a second current source coupled to the first current source to generate reference voltage, a resistor coupled to the second current source to enable generation of the reference voltage, a capacitor coupled to the first current source that is charged based on the charging current, a comparator responsive to voltage corresponding to the capacitor and the reference voltage to generate output voltage, a peak detector coupled to the capacitor to generate peak voltage, an error detector coupled to the peak detector and the second current source to generate an error based on the peak voltage and the reference voltage, and a controller coupled to the error detector to control one of the charging current, offset voltage input to the comparator, and capacitance of the capacitor.Type: ApplicationFiled: November 22, 2011Publication date: December 20, 2012Applicant: Cosmic Circuits Private LimitedInventors: Prasenjit Bhowmik, Rishi Mathur, Sriram Ganesan, Sunil Rajan
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Patent number: 8106706Abstract: A method for biasing a MOS transistor includes AC coupling an input signal from an amplifier stage to a gate of the MOS transistor. The method includes connecting a pair of diodes in an opposing parallel configuration to a bias transistor and a current source. Further, the method includes generating a DC bias voltage through the bias transistor and the current source. The method also includes clamping the voltage at drain of the bias transistor to a fixed voltage by a clamping circuit. Further, the method includes coupling the DC bias voltage to the gate of the MOS transistor through the pair of diodes.Type: GrantFiled: May 9, 2009Date of Patent: January 31, 2012Assignee: Cosmic Circuits Private LimitedInventors: Prakash Easwaran, Prasenjit Bhowmik, Sumeet Mathur
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Patent number: 7868688Abstract: A current filter circuit is provided. The current filter circuit comprises a source transistor comprising a drain, a gate, and a source. The source of the source transistor is coupled to a reference voltage terminal, the gate of the source transistor is coupled to the gate of a mirror transistor, and the drain of the source transistor is coupled to a reference current source. The mirror transistor comprises a drain, a gate, and a source. The source of the mirror transistor is coupled to the reference voltage terminal, the gate is coupled to the gate of the source transistor, and the drain is coupled to a load. The current filter circuit comprises a low pass filter for filtering noise. The current filter circuit also comprises an impedance reduction circuit coupled to the drain of the mirror transistor for reducing bandwidth of the current filter circuit.Type: GrantFiled: May 9, 2009Date of Patent: January 11, 2011Assignee: Cosmic Circuits Private LimitedInventors: Prakash Easwaran, Prasenjit Bhowmik, Sumeet Mathur
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Patent number: 7821436Abstract: A system and method for reducing the power dissipated in an Analog to Digital Converter (ADC). The method includes the steps of: receiving a residue output from a previous phase of a plurality of clock phases where the plurality of clock phases includes a sample-and-hold phase and an amplifying phase for sampling and amplifying an analog input signal respectively, eliminating an effect of load on a residue amplifier when amplifying the residue output to generate an amplified residue output in the amplifying phase, and eliminating an effect of small feedback factor when sampling the amplified residue output in the sample-and-hold phase. Power advantage is achieved by sharing the load on the residue amplifier across the sample-and-hold phase and the amplifying phase rather than being fully present in any one of the clock phases. The present invention also provides a method for reducing the number of comparators used in ADCs.Type: GrantFiled: June 9, 2007Date of Patent: October 26, 2010Assignee: Cosmic Circuits Private LimitedInventors: Venkatesh Teeka Srinvasa Setty, Chandrashekar Lakshminarayanan, Prasun Kali Bhattacharya, Prasenjit Bhowmik, Chakravarthy Srinivasan, Mukesh Khatri, Sanjeeb Kumar Ghosh, Sumanth Chakkirala, Sundararajan Krishnan, Prakash Easwaran
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Publication number: 20100164606Abstract: A method for biasing a MOS transistor includes AC coupling an input signal from an amplifier stage to a gate of the MOS transistor. The method includes connecting a pair of diodes in an opposing parallel configuration to a bias transistor and a current source. Further, the method includes generating a DC bias voltage through the bias transistor and the current source. The method also includes clamping the voltage at drain of the bias transistor to a fixed voltage by a clamping circuit. Further, the method includes coupling the DC bias voltage to the gate of the MOS transistor through the pair of diodes.Type: ApplicationFiled: May 9, 2009Publication date: July 1, 2010Applicant: COSMIC CIRCUITS PRIVATE LIMITEDInventors: Prakash EASWARAN, Prasenjit BHOWMIK, Sumeet MATHUR
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Publication number: 20100164611Abstract: A current filter circuit is provided. The current filter circuit comprises a source transistor comprising a drain, a gate, and a source. The source of the source transistor is coupled to a reference voltage terminal, the gate of the source transistor is coupled to the gate of a mirror transistor, and the drain of the source transistor is coupled to a reference current source. The mirror transistor comprises a drain, a gate, and a source. The source of the mirror transistor is coupled to the reference voltage terminal, the gate is coupled to the gate of the source transistor, and the drain is coupled to a load. The current filter circuit comprises a low pass filter for filtering noise. The current filter circuit also comprises an impedance reduction circuit coupled to the drain of the mirror transistor for reducing bandwidth of the current filter circuit.Type: ApplicationFiled: May 9, 2009Publication date: July 1, 2010Applicant: COSMIC CIRCUITS PRIVATE LIMITEDInventors: Prakash EASWARAN, Prasenjit BHOWMIK, Sumeet MATHUR
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Patent number: 7675333Abstract: A Delay Locked Loop (DLL) and method for generating multiple equally spaced phases over a wide frequency range is disclosed. The DLL includes a delay line, and a control module. The delay line receives a reference clock signal and outputs a final delay clock signal in response to the reference clock signal. The delay line includes a plurality of delay cells connected in series. The plurality of delay cells generate a plurality of delay clock signals having equally spaced phases. The control module generates a phase control signal based on counting a number of pulses of the reference clock signal that are input to the delay line before occurrence of a first corresponding pulse of the final delay clock signal.Type: GrantFiled: June 10, 2007Date of Patent: March 9, 2010Assignee: Cosmic Circuits Private LimitedInventors: Prasenjit Bhowmik, Sundararajan Krishnan, Sriram Ganesan