Abstract: Embodiments described include straining transistor quantum well (QW) channel regions with metal source/drains, and conformal regrowth source/drains to impart a uni-axial strain in a MOS channel region. Removed portions of a channel layer may be filled with a junction material having a lattice spacing different than that of the channel material to causes a uni-axial strain in the channel, in addition to a bi-axial strain caused in the channel layer by a top barrier layer and a bottom buffer layer of the quantum well.

Abstract: Embodiments of the present invention describe a semiconductor device having an buffer structure and methods of fabricating the buffer structure. The buffer structure is formed between a substrate and a quantum well layer to prevent defects in the substrate and quantum well layer due to lattice mismatch. The buffer structure comprises a first buffer layer formed on the substrate, a plurality of blocking members formed on the first buffer layer, and second buffer formed on the plurality of blocking members. The plurality of blocking members prevent the second buffer layer from being deposited directly onto the entire first buffer layer so as to minimize lattice mismatch and prevent defects in the first and second buffer layers.

Abstract: In one embodiment, the present invention includes an apparatus having a substrate, a buried oxide layer formed on the substrate, a silicon on insulator (SOI) core formed on the buried oxide layer, a compressive strained quantum well (QW) layer wrapped around the SOI core, and a tensile strained silicon layer wrapped around the QW layer. Other embodiments are described and claimed.

Abstract: A semiconductor structure may include a semiconductor bulk region with a gate stack on the semiconductor bulk region. The source region and the drain region in the semiconductor bulk region may be located on opposing sides of a channel region below the gate stack. An interfacial layer coupled to the channel region may modify a workfunction of a metal-semiconductor contact. In a MOSFET, the metal-semiconductor contact may be between a metal contact and the source region and the drain region. In a Schottky barrier-MOSFET, the metal-semiconductor contact may be between a silicide region in the source region and/or the drain region and the channel region. The interfacial layer may use a dielectric-dipole mitigated scheme and may include a conducting layer and a dielectric layer. The dielectric layer may include lanthanum oxide or aluminum oxide used to tune the workfunction of the metal-semiconductor contact.

Abstract: A microelectronic device includes a tunneling pocket within an asymmetrical semiconductive body including source- and drain wells. The tunneling pocket is formed by a self-aligned process by removing a dummy gate electrode from a gate spacer and by implanting the tunneling pocket into the semiconductive body or into an epitaxial film that is part of the semiconductive body.

Abstract: Embodiments described include straining transistor quantum well (QW) channel regions with metal source/drains, and conformal regrowth source/drains to impart a uni-axial strain in a MOS channel region. Removed portions of a channel layer may be filled with a junction material having a lattice spacing different than that of the channel material to causes a uni-axial strain in the channel, in addition to a bi-axial strain caused in the channel layer by a top barrier layer and a bottom buffer layer of the quantum well.

Abstract: Electronic apparatus, systems, and methods of forming such electronic apparatus and systems include non-insulating nanocrystals disposed on a dielectric stack, where the non-insulating nanocrystals are arranged to store electric charge. The dielectric stack includes two dielectric layers having different electron barriers such that the non-insulating nanocrystals may be disposed on the dielectric layer having the lower electron barrier.

Abstract: Embodiments described include straining transistor quantum well (QW) channel regions with metal source/drains, and conformal regrowth source/drains to impart a uni-axial strain in a MOS channel region. Removed portions of a channel layer may be filled with a junction material having a lattice spacing different than that of the channel material to causes a uni-axial strain in the channel, in addition to a bi-axial strain caused in the channel layer by a top barrier layer and a bottom buffer layer of the quantum well.

Abstract: Embodiments of the present invention describe a semiconductor device having an buffer structure and methods of fabricating the buffer structure. The buffer structure is formed between a substrate and a quantum well layer to prevent defects in the substrate and quantum well layer due to lattice mismatch. The buffer structure comprises a first buffer layer formed on the substrate, a plurality of blocking members formed on the first buffer layer, and second buffer formed on the plurality of blocking members. The plurality of blocking members prevent the second buffer layer from being deposited directly onto the entire first buffer layer so as to minimize lattice mismatch and prevent defects in the first and second buffer layers.

Abstract: Embodiments described include straining transistor quantum well (QW) channel regions with metal source/drains, and conformal regrowth source/drains to impart a uni-axial strain in a MOS channel region. Removed portions of a channel layer may be filled with a junction material having a lattice spacing different than that of the channel material to causes a uni-axial strain in the channel, in addition to a bi-axial strain caused in the channel layer by a top barrier layer and a bottom buffer layer of the quantum well.

Abstract: Transistors having a Hafnium-Silicon gate electrode and high-k dielectric are disclosed. A workpiece is provided having a gate dielectric formed over the workpiece, and a gate formed over the gate dielectric. The gate may comprise a layer of a combination of Hf and Si. The layer of the combination of Hf and Si of the gate establishes the threshold voltage Vt of the transistor. The transistor may comprise a single NMOS transistor or an NMOS transistor of a CMOS device.

Abstract: The method for determining the thickness of a dielectric layer according to the invention comprises the step of providing an electrically conductive body having a dielectric layer which is separated from the electrically conductive body by at least a further dielectric layer and a surface of which is exposed. Onto the exposed surface an electric charge is deposited, thereby inducing an electric potential difference between the exposed surface and the electrically conductive body. An electrical parameter relating to the electric potential difference is determined and a measurement is performed to obtain additional measurement data relating to the thickness of the dielectric layer and/or to the thickness of the further dielectric layer. In this way the thickness of the dielectric layer and/or of the further dielectric layer is determined. The method of manufacturing an electric device comprises this method for determining the thickness of a dielectric layer.

Abstract: A microelectronic device includes a tunneling pocket within an asymmetrical semiconductive body including source- and drain wells. The tunneling pocket is formed by a self-aligned process by removing a dummy gate electrode from a gate spacer and by implanting the tunneling pocket into the semiconductive body or into an epitaxial film that is part of the semiconductive body.

Abstract: A method to form a strain-inducing semiconductor region comprising three or more species of charge-neutral lattice-forming atoms is described. In one embodiment, formation of a strain-inducing semiconductor region, comprising three or more species of charge-neutral lattice-forming atoms, laterally adjacent to a crystalline substrate results in a uniaxial strain imparted to the crystalline substrate. Thus, a strained crystalline substrate may be provided. In another embodiment, a semiconductor region with a crystalline lattice of three or more species of charge-neutral lattice-forming atoms imparts a strain to a crystalline substrate, wherein the lattice constant of the semiconductor region is different from that of the crystalline substrate.

Abstract: Methods of forming dual metal gates and the gates so formed are disclosed. A method may include forming a first metal (e.g., NMOS metal) layer on a gate dielectric layer and a second metal (e.g., PMOS metal) layer on the first metal layer, whereby the second metal layer alters a work function of the first metal layer (to form PMOS metal). The method may remove a portion of the second metal layer to expose the first metal layer in a first region; form a silicon layer on the exposed first metal layer in the first region and on the second metal layer in a second region; and form the dual metal gates in the first and second regions. Since the gate dielectric layer is continuously covered with the first metal, it is not exposed to the damage from the metal etch process.

Abstract: Nanocrystal structures formed using atomic layer deposition (ALD) processes are useful in the formation of integrated circuits such as memory devices. Rather than continuing the ALD process until a continuous layer is formed, the ALD process is halted prematurely to leave a discontinuous formation of nanocrystals which are then capped by a different material, thus forming a layer with a discontinuous portion and a bulk portion. Such nanocrystals can serve as charge-storage sites within the bulk portion, and the resulting structure can serve as a floating gate of a floating-gate memory cell. A floating gate may contain one or more layers of such nanocrystal structures.

Abstract: A process for forming defect-free source and drain extensions for a MOSFET built on a germanium based channel region deposits a first silicon germanium layer on a semiconductor substrate, deposits a gate dielectric layer on the silicon germanium layer, and deposits a gate electrode layer on the gate dielectric layer. A dry etch chemistry etches those layers to form a gate electrode, a gate dielectric, and a silicon germanium channel region on the semiconductor substrate. Next, an ion implantation process forms halo implant regions that consume portions of the silicon germanium channel region and the semiconductor substrate. Finally, an in-situ doped epitaxial deposition process grows a pair of silicon germanium layers having LDD regions. The silicon germanium layers are adjacent to the silicon germanium channel region and the halo implant regions do not damage any portion of the silicon germanium layers.

Abstract: Reducing defects in semiconductor quantum well structures is generally described. In one example, an apparatus includes a semiconductor substrate including silicon, a buffer film epitaxially grown on the semiconductor substrate, the buffer film comprising silicon, germanium, and an impurity, and a first semiconductor film epitaxially grown on the buffer film wherein a lattice mismatch exists between the semiconductor substrate and the first semiconductor film and wherein the impurity disrupts lattice structure dislocation gliding in at least the first semiconductor film.

Abstract: A process for forming defect-free source and drain extensions for a MOSFET built on a germanium based channel region deposits a first silicon germanium layer on a semiconductor substrate, deposits a gate dielectric layer on the silicon germanium layer, and deposits a gate electrode layer on the gate dielectric layer. A dry etch chemistry etches those layers to form a gate electrode, a gate dielectric, and a silicon germanium channel region on the semiconductor substrate. Next, an ion implantation process forms halo implant regions that consume portions of the silicon germanium channel region and the semiconductor substrate. Finally, an in-situ doped epitaxial deposition process grows a pair of silicon germanium layers having LDD regions. The silicon germanium layers are adjacent to the silicon germanium channel region and the halo implant regions do not damage any portion of the silicon germanium layers.

Abstract: Devices comprising, and method for fabricating, a MOSFET with a metal gate electrode are disclosed. In one embodiment, the MOSFET includes a first doped region configured to receive current from a current source, a second doped region configured to drain current from the first doped region when an electric field is modified between the first doped region and the second doped region, and a gate electrode configured to modify the electric field. The gate electrode may include a high-k layer, a hafnium-based metal layer formed above the high-k layer, and a polysilicon layer formed above the hafnium-based metal layer. In a further embodiment, the gate electrode further comprises a titanium-based metal layer formed between the hafnium-based metal layer and the polysilicon layer.