Abstract: In one embodiment, the present invention includes a method for forming a transistor that includes forming a first buffer layer of silicon germanium tin (SiGe(Sn)) on a silicon (Si) substrate, forming a barrier layer on the first buffer layer, the barrier layer comprising silicon germanium (Si1?xGex), and forming a quantum well (QW) layer on the barrier layer including a lower QW barrier layer formed of silicon germanium carbon (Si1?yGey(C)), a strained QW channel layer formed of germanium on the lower QW layer, and an upper QW barrier layer on the strained QW channel layer formed of Si1?zGez(C). Other embodiments are described and claimed.

Abstract: In one embodiment, the present invention includes an apparatus having a substrate, a buried oxide layer formed on the substrate, a silicon on insulator (SOI) core formed on the buried oxide layer, a compressive strained quantum well (QW) layer wrapped around the SOI core, and a tensile strained silicon layer wrapped around the QW layer. Other embodiments are described and claimed.

Abstract: In one embodiment, the present invention includes a method for forming a transistor that includes forming a first buffer layer of silicon germanium tin (SiGe(Sn)) on a silicon (Si) substrate, forming a barrier layer on the first buffer layer, the barrier layer comprising silicon germanium (Si1-xGex), and forming a quantum well (QW) layer on the barrier layer including a lower QW barrier layer formed of silicon germanium carbon (Si1-yGey(C)), a strained QW channel layer formed of germanium on the lower QW layer, and an upper QW barrier layer on the strained QW channel layer formed of Si1-zGez(C). Other embodiments are described and claimed.

Abstract: Transistors and methods of manufacture thereof are disclosed. A workpiece is provided, a gate dielectric is formed over the workpiece, and a gate is formed over the gate dielectric by exposing the workpiece to a precursor of hafnium (Hf) and a precursor of silicon (Si). The gate may comprise a layer of a combination of Hf and Si. The layer of the combination of Hf and Si of the gate establishes the threshold voltage Vt of the transistor. The transistor may comprise a single NMOS transistor or an NMOS transistor of a CMOS device.

Abstract: Electronic apparatus, systems, and methods of forming such electronic apparatus and systems include non-insulating nanocrystals disposed on a dielectric stack, where the non-insulating nanocrystals are arranged to store electric charge. The dielectric stack includes two dielectric layers having different electron barriers such that the non-insulating nanocrystals may be disposed on the dielectric layer having the lower electron barrier.

Abstract: Transistors and methods of manufacture thereof are disclosed. A workpiece is provided, a gate dielectric is formed over the workpiece, and a gate is formed over the gate dielectric by exposing the workpiece to a precursor of hafnium (Hf) and a precursor of silicon (Si). The gate includes and include respectively a layer of a combination of Hf and Si. The layer of the combination of Hf and Si of the gate establishes the threshold voltage Vt of the transistor. The transistor may includes and include respectively a single NMOS transistor or an NMOS transistor of a CMOS device.

Abstract: Methods for fabricating two metal gate stacks with varying work functions for complementary metal oxide semiconductor (CMOS) devices are provided A first metal layer may be deposited onto a gate dielectric, followed by the deposition of a second metal layer, where the second metal layer modulated the work function of the first metal layer. The second metal layer and subsequently etch, exposing a portion of the first metal layer. A third metal layer may be deposited on the etched second metal layer and the exposed first metal layer, where the third metal layer may modulate the work function of the exposed first metal layer. Subsequent fabrication techniques may be used to define the gate stack.

Abstract: A method to form a strain-inducing semiconductor region comprising three or more species of charge-neutral lattice-forming atoms is described. In one embodiment, formation of a strain-inducing semiconductor region, comprising three or more species of charge-neutral lattice-forming atoms, laterally adjacent to a crystalline substrate results in a uniaxial strain imparted to the crystalline substrate. Thus, a strained crystalline substrate may be provided. In another embodiment, a semiconductor region with a crystalline lattice of three or more species of charge-neutral lattice-forming atoms imparts a strain to a crystalline substrate, wherein the lattice constant of the semiconductor region is different from that of the crystalline substrate.

Abstract: The method for determining a dielectric layer thickness according to the invention comprises the step of providing an electrically conductive body (11) having a dielectric layer (13) which is separated from the electrically conductive body (11) by at least a further dielectric layer (3) and a surface (15) of which is exposed. Onto the exposed surface (15) an electric charge is deposited thereby inducing an electrical potential difference between the exposed surface (15) and the electrically conductive body (11). An electrical parameter relating to the electrical potential difference is determined and a measurement is performed to obtain additional measurement data relating to a thickness of the dielectric layer (13) and/or to a thickness of the further dielectric layer (3). In this way the thickness of the dielectric layer (13) and/or of the further dielectric layer (3) is determined. The method of manufacturing an electric device (100) comprises this method for determining a dielectric layer thickness.

Abstract: The method for determining the thickness of a dielectric layer according to the invention comprises the step of providing an electrically conductive body (11) having a dielectric layer (13) which is separated from the electrically conductive body (11) by at least a further dielectric layer (3) and a surface (15) of which is exposed. Onto the exposed surface (15) an electric charge is deposited, thereby inducing an electric potential difference between the exposed surface (15) and the electrically conductive body (11). An electrical parameter relating to the electric potential difference is determined and a measurement is performed to obtain additional measurement data relating to the thickness of the dielectric layer (13) and/or to the thickness of the further dielectric layer (3). In this way the thickness of the dielectric layer (13) and/or of the further dielectric layer (3) is determined.

Abstract: Methods for fabricating two metal gate stacks with varying work functions for complementary metal oxide semiconductor (CMOS) devices are provided A first metal layer may be deposited onto a gate dielectric, followed by the deposition of a second metal layer, where the second metal layer modulated the work function of the first metal layer. The second metal layer and subsequently etch, exposing a portion of the first metal layer. A third metal layer may be deposited on the etched second metal layer and the exposed first metal layer, where the third metal layer may modulate the work function of the exposed first metal layer. Subsequent fabrication techniques were used to define the gate stack.

Abstract: Transistors and methods of manufacture thereof are disclosed. A workpiece is provided, a gate dielectric is formed over the workpiece, and a gate is formed over the gate dielectric by exposing the workpiece to a precursor of hafnium (Hf) and a precursor of silicon (Si). The gate comprises a layer of a combination of Hf and Si. The layer of the combination of Hf and Si of the gate establishes the threshold voltage Vt of the transistor. The transistor may comprise a single NMOS transistor or an NMOS transistor of a CMOS device.

Abstract: The method for determining the thickness of a dielectric layer according to the invention comprises the step of providing an electrically conductive body (11) having a dielectric layer (13) which is separated from the electrically conductive body (11) by at least a further dielectric layer (3) and a surface (15) of which is exposed. Onto the exposed surface (15) an electric charge is deposited, thereby inducing an electric potential difference between the exposed surface (15) and the electrically conductive body (11). An electrical parameter relating to the electric potential difference is determined and a measurement is performed to obtain additional measurement data relating to the thickness of the dielectric layer (13) and/or to the thickness of the further dielectric layer (3). In this way the thickness of the dielectric layer (13) and/or of the further dielectric layer (3) is determined.