Abstract: A system and method of scheduling packets in a multi-threaded, multiprocessor network architecture provides enhanced speed and performance. The architecture involves a scheduler thread that transitions between queues in response to a depletion of queues by a weighted amount, a plurality of transmit threads that deplete the queues by the size of packets transmitted and a plurality of receive threads that initialize the weights for idle queues.

Abstract: Methods, software and systems to determine channel ownership and physical block location within the channel in non-uniformly distributed DRAM configurations and also to detect in-range memory address matches are presented. A first method, which may also be implemented in software and/or hardware, allocates memory non-uniformly between a number of memory channels, determines a selected memory channel from the memory channels for a program address, and maps the program address to a physical address within the selected memory channel. A second method, which may also be implemented in software and/or hardware, designates a range of memory to perform address matching, monitors memory accesses and when a memory access occurs with the specified range, perform a particular function.

Abstract: A memory controller that includes an interface to a first memory and an interface to a bus coupling the memory controller to at least one processor. The controller also includes circuitry, responsive to read and write commands received over the bus from the at least one processor, to shift data by an amount identified by at least some of the read and write commands.

Abstract: In general, in one aspect, the disclosure describes a method of assembling a packet in memory. The method includes reading data included in a first segment of a packet divided into multiple segments and issuing a command to a memory controller that causes the memory controller to shift and write a subset of the read data to a memory coupled to the memory controller. The method also includes saving the remainder of the read data as a first residue, retrieving data included in a second segment of the packet, and writing at least a portion of the retrieved data and the first residue to the memory.

Abstract: According to some embodiments, systems an apparatuses may have a communication path to exchange information packets. A processor may process information packets. A buffer pool cache local to the processor may store free buffer handles for information packets when the buffer pool cache local to the processor is not full. A non-local memory may store the free buffer handles for information packets when the buffer pool cache local to the processor is full.

Abstract: A method executed in a computing device for scheduling data packet transfer, the method includes receiving a first and second bit, the first bit indicates if a first digital device is ready to transfer a first data packet, the second bit indicates if a second digital device is ready to transfer a second data packet, receiving a binary number that identifies the first bit, determining the first digital device is ready to transfer the first data packet based on the binary number identifying the first bit, and incrementing the binary number to identify the second bit.

Abstract: A method and system of enqueueing and dequeueing packets in a multi-threaded environment provide enhanced speed and performance. An availability of a queue is determined, where the queue is shared by a plurality of receive threads and has an associated produce index. If the queue is determined to be available, the produce index is incremented while the produce index is locked. On the other hand, an incoming packet is written to the queue while the produce index is unlocked. It is further determined whether data is stored in a queue of an off-chip memory of a network processor based on a produce count and a consume count. The produce count and the consume are stored in an on-chip memory of the network processor.

Abstract: Embodiments of the present invention relate to improving the efficiency of packet enqueue, drop or mark processing in networks. Operations involved in computing an average queue size for making enqueue, drop or mark decisions utilize binary shift operations for computational efficiency. Operations used in computing a probability value used in making drop or mark decisions are also made more efficient.

Abstract: A system and method of scheduling packets in a multi-threaded, multiprocessor network architecture provides enhanced speed and performance. The architecture involves a scheduler thread that transitions between queues in response to a depletion of queues by a weighted amount, a plurality of transmit threads that deplete the queues by the size of packets transmitted and a plurality of receive threads that initialize the weights for idle queues.