Patents by Inventor Prateek SINGH
Prateek SINGH has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 12681870Abstract: Systems and methods for load compensation are presented to support a wide range of capacitive loads on a pad coupled to an I/O transmitter. The I/O transmitter includes I/O architecture coupled to a pad and a calibration circuit coupled to the I/O architecture. The calibration circuit includes sensing circuitry, pulse generation circuitry coupled to the sensing circuitry and control bit generation circuitry coupled to the pulse generation circuitry. The control bit generation circuitry generates control bits proportional to load variations detected at the pad and feeds the control bits to the I/O architecture to modulate rise and fall times of pulsed signals at the pad.Type: GrantFiled: July 29, 2024Date of Patent: July 14, 2026Assignee: Synopsys, Inc.Inventors: Kailash Kumar, Prateek Singh, Manoj Kumar
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Patent number: 12644084Abstract: An apparatus for cell cultivation includes first reservoir structure, second reservoir structure and a membrane. The first reservoir structure has first matrix of pitted reservoirs and the second reservoir structure has second matrix of pitted reservoirs. The first reservoir structure, second reservoir structure and the membrane are arranged as a stack. The membrane is arranged between first reservoir structure and second reservoir structure, and the first matrix of pitted reservoirs is aligned with the second matrix of pitted reservoirs to couple pitted reservoirs of the first matrix of pitted reservoirs together with pitted reservoirs of the second matrix of pitted reservoirs via the membrane.Type: GrantFiled: May 11, 2021Date of Patent: June 2, 2026Assignee: Finnadvance OyInventors: Tuomas Nurmi, Nguyen Tuan, Prateek Singh, Minna Kihlström, Jari Moilanen
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Publication number: 20260117161Abstract: The present disclosure relates a cell culture apparatus, a method for affecting a cell culture by using the cell culture apparatus, uses of the cell culture apparatus, and a cell culture incubator comprising the cell culture apparatus.Type: ApplicationFiled: September 9, 2022Publication date: April 30, 2026Applicant: Finnadvance OYInventors: Prateek Singh, Hoang Tuan Nguyen
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Publication number: 20250371268Abstract: A method may receive a text string of an utterance. A method may tokenize the utterance into a plurality of tokens. A method may transform the plurality of tokens into a plurality of feature vectors. A method may assign an entity label to each of the plurality of feature vectors. A method may resolve each feature vector of the plurality of feature vectors to a corresponding standardized value of a database query language.Type: ApplicationFiled: August 13, 2025Publication date: December 4, 2025Inventors: Hanoz BHATHENA, Prateek SINGH, Aviral JOSHI
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Publication number: 20250361471Abstract: The present disclosure relates to a cell culture apparatus provided with one or more biologic scaffolds (e.g., tissue-specific, bone-specific and/or organ-specific scaffolds), a method for cell cultivation by using the cell culture apparatus, and a cell culture incubator comprising the cell culture apparatus. More specifically, the cell culture apparatus comprises a plurality of cell culture modules arranged adjacent to each other. Each cell culture module comprises two or more culture medium reservoirs connected by two or more flow channels to a top-loaded chamber. The top-loaded chamber has a porous biologic scaffold arranged therein such that the biologic scaffold is at least partly exposed to a culture medium flow passing between the culture medium reservoirs through the top-loaded chamber. The apparatus thus configured may facilitate efficient biologic scaffold-assisted cell cultivation in vitro.Type: ApplicationFiled: June 2, 2023Publication date: November 27, 2025Applicant: FINNADVANCE OYInventors: Prateek SINGH, Hoang Tuan NGUYEN
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Publication number: 20250354099Abstract: Disclosed is a cell culture apparatus and a method. The apparatus comprises one or more cell culture modules. The one or more cell culture modules comprise a first culture medium reservoir. a second culture medium reservoir, a first open-top well configured for cell cultivation. a second open-top well and a microfluidic channel configured to provide a fluid connection from the first culture medium reservoir to the second culture medium reservoir through the first open-top well and the second open-top well. The second open-top well is configured to receive a flow restrictor to at least partially block the fluid connection through the second open-top well.Type: ApplicationFiled: May 26, 2023Publication date: November 20, 2025Applicant: FINNADVANCE OYInventors: Prateek SINGH, Hoang Tuan NGUYEN
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Publication number: 20250354105Abstract: A membrane structure for stimulating and sensing a biological material is provided, which comprises a porous membrane having at least one array of needles on its top and/or bottom surface, without closing through pores of the membrane. Each needle of the at least one array of needles is configured to penetrate the biological material, is made of a non-conducting material and at least partly coated with a conducting electrode. By using the membrane structure thus configured, it is possible to apply an electrical stimulus to the biological material and take response measurements. Moreover, the presence of the through pores in the membrane structure allows the biological material (penetrated by the needles) to be perfused or vascularized through a microfluidic channel with which the membrane structure may be brought into contact. In other embodiments, a cell culture plate and a microfluidic device are provided, each of which incorporates the membrane structure.Type: ApplicationFiled: June 2, 2023Publication date: November 20, 2025Applicant: FINNADVANCE OYInventors: Prateek SINGH, Hoang Tuan NGUYEN
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Patent number: 12393623Abstract: A method may receive a text string of an utterance. A method may tokenize the utterance into a plurality of tokens. A method may transform the plurality of tokens into a plurality of feature vectors. A method may assign an entity label to each of the plurality of feature vectors. A method may resolve each feature vector of the plurality of feature vectors to a corresponding standardized value of a database query language.Type: GrantFiled: February 14, 2023Date of Patent: August 19, 2025Assignee: JPMORGAN CHASE BANK, N.A.Inventors: Hanoz Bhathena, Prateek Singh, Aviral Joshi
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Patent number: 12367911Abstract: A dynamic gate control signal generator circuit includes a pad configured to produce an output voltage, a reference generator configured to receive a supply voltage (VDDIO) and produce, based on the supply voltage, a first reference voltage signal and a second reference voltage signal, and a pad tracker circuit coupled to the reference generator, the pad tracker circuit configured to receive the output voltage of the pad and limit a high voltage of the pad to the second reference voltage signal. The dynamic gate control signal generator circuit further includes a first clamper circuit coupled to the pad tracker, the first clamper circuit configured to receive an output voltage signal from the pad tracker circuit and generate, based on the output voltage signal, a dynamic gate control signal that toggles between the first reference voltage signal and the second reference voltage signal.Type: GrantFiled: March 1, 2023Date of Patent: July 22, 2025Assignee: Synopsys, Inc.Inventors: Prateek Singh, Kailash Kumar
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Patent number: 12265121Abstract: In accordance with an embodiment, a method for operating a Pseudo-Random Pattern Generator (PRPG) based scan test system includes: generating test patterns using a Pseudo-Random Pattern Generator (PRPG), generating the test patterns including clocking the PRPG using a first clock signal; loading the test patterns into a plurality of scan chains coupled to the PRPG; modifying a bit distribution of the generated test patterns with respect to the plurality of scan chains by freezing at least one clock cycle of the first clock signal while a second clock signal is active or freezing at least one clock cycle of the second clock signal while the first clock signal is active; shifting the loaded test patterns using the second clock signal; applying the test patterns to a circuit under test (CUT) through the plurality of scan chains; and capturing response patterns generated by the CUT in the plurality of scan chains.Type: GrantFiled: May 23, 2023Date of Patent: April 1, 2025Assignee: STMicroelectronics International N.V.Inventors: Sandeep Jain, Shalini Pathak, Prateek Singh
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Patent number: 12204782Abstract: According to an embodiment, a method for testing and repairing local memory in a hardware accelerator from a one-time programmable memory (OTP) is provided. The method includes asserting a grant signal, a loading of a first repair data for a sub-set of the local memory associated with a main-controller from a first partition of the OTP memory, communicating a status signal after completion of the loading indicating a completion of the loading, and de-asserting the grant signal in response to receiving the status signal.Type: GrantFiled: June 20, 2023Date of Patent: January 21, 2025Assignee: STMicroelectronics International N.V.Inventors: Urmishkumar Karsanbhai Patel, Danish Hasan Syed, Prateek Singh
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Patent number: 12189729Abstract: A method for processing multimedia content for authentication and authenticating the multimedia content includes registering a scheduled event, creating a mapping between the scheduled event and a registrant of the scheduled event and in response to creating the mapping between the scheduled event and the registrant, issuing a request to add a block in a blockchain for the mapping. The method also includes in response to the request, receiving, a block identifier, generating a start code for one or more modulation schemes based on the block identifier, receiving multimedia content generated based on the scheduled event and modifying the multimedia content based on the one or more modulation schemes for distribution of the multimedia content.Type: GrantFiled: July 19, 2022Date of Patent: January 7, 2025Assignee: Avaya Management L.P.Inventors: Prateek Singh, Divyarajsinh Jadeja, Mittali Jangid
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Patent number: 12192669Abstract: A method for auto focus on a speaker during a communication session includes receiving video captured of a scene that includes a plurality of images of participants to the communication session, identifying the plurality of images of the participants in the video captured of the scene, recognizing audio from at least one of the participants, detecting facial movement in one of the images of the plurality of images and equating the recognized audio to the detected movement in the one of the images of the plurality of images. The method also includes selecting the one of the images of the plurality of images as a speaker based on the equated recognized audio to the detected movement in the one of the images, zooming in on the speaker and filtering out a remainder of the images of the plurality of images.Type: GrantFiled: June 8, 2022Date of Patent: January 7, 2025Assignee: Avaya Management L.P.Inventors: Prateek Singh, Divyarajsinh Jadeja, Mittali Jangid, Dean Beightol
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Publication number: 20240427514Abstract: According to an embodiment, a method for testing and repairing local memory in a hardware accelerator from a one-time programmable memory (OTP) is provided. The method includes asserting a grant signal, a loading of a first repair data for a sub-set of the local memory associated with a main-controller from a first partition of the OTP memory, communicating a status signal after completion of the loading indicating a completion of the loading, and de-asserting the grant signal in response to receiving the status signal.Type: ApplicationFiled: June 20, 2023Publication date: December 26, 2024Inventors: Urmishkumar Karsanbhai Patel, Danish Hasan Syed, Prateek Singh
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Publication number: 20240393393Abstract: In accordance with an embodiment, a method for operating a Pseudo-Random Pattern Generator (PRPG) based scan test system includes: generating test patterns using a Pseudo-Random Pattern Generator (PRPG), generating the test patterns including clocking the PRPG using a first clock signal; loading the test patterns into a plurality of scan chains coupled to the PRPG; modifying a bit distribution of the generated test patterns with respect to the plurality of scan chains by freezing at least one clock cycle of the first clock signal while a second clock signal is active or freezing at least one clock cycle of the second clock signal while the first clock signal is active; shifting the loaded test patterns using the second clock signal; applying the test patterns to a circuit under test (CUT) through the plurality of scan chains; and capturing response patterns generated by the CUT in the plurality of scan chains.Type: ApplicationFiled: May 23, 2023Publication date: November 28, 2024Inventors: Sandeep Jain, Shalini Pathak, Prateek Singh
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Publication number: 20240384241Abstract: A cell culture apparatus comprises adjacent cell culture modules with each module including culture medium reservoirs connected by flow channels. The flow channels go through a basal chamber under an apical chamber. These chambers are separated by a porous membrane. The basal chamber has a bottom part higher than a bottom part of each of the reservoirs. Flows of culture media may be perfused and regulated between the reservoirs in each module by placing the apparatus on a rocking platform or connecting the apparatus to a pneumatic pump. The apparatus may cultivate cells of the same or different types on the basal surface of the porous membranes in the modules under unform and controlled in vitro conditions. Deposition of cells on the basal surface of the porous membranes may be provided without having to invert the apparatus and to use high concentrations of the cells in the culture medium.Type: ApplicationFiled: September 9, 2022Publication date: November 21, 2024Applicant: Finnadvance OYInventor: Prateek Singh
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Patent number: 12119827Abstract: An electric circuit and a method for filtering glitches are described. The electric circuit includes a filter, an inverter circuit, and a reset circuit. The inverter circuit is electrically coupled to an output of the filter. The reset circuit is electrically coupled to the output of the filter. The reset circuit pulls the output of the filter high when an input signal to the electric circuit and the output of the inverter circuit are both low, pulls the output of the filter low when the input signal to the electric circuit and the output of the inverter circuit are both high, and passes the output of the filter when (i) the input signal to the electric circuit is high and the output of the inverter circuit is low or (ii) the input signal to the electric circuit is low and the output of the inverter circuit is high.Type: GrantFiled: December 22, 2022Date of Patent: October 15, 2024Assignee: Synopsys, Inc.Inventors: Kailash Kumar, Prateek Singh, Akhil Thotli, Sriram Kumar Jayanthi, Rahul Gupta
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Patent number: 12111955Abstract: The technology disclosed herein enables automatic obscuration of a portion of a view shared during a screen sharing session. In a particular embodiment, a method includes receiving a view displayed by a first user system to a first user. The method further includes identifying a portion of the view not to be shared and obscuring the portion of the view to generate a shared view. Also, the method includes transmitting the shared view to a second user system over a real-time screen sharing session, wherein the second user system displays the shared view to a second user.Type: GrantFiled: October 14, 2021Date of Patent: October 8, 2024Assignee: Avaya Management L.P.Inventors: Vijaykumar Bhayani, Divyarajsinh Jadeja, Prateek Singh
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Patent number: 12074597Abstract: A circuit provides fail safe protection of an input/output (I/O) circuit of a chip. The I/O circuit comprises an I/O pad connected to one or more other chips via an I/O bus. The circuit comprise a supply and failsafe detector component. The supply and failsafe detector component generates an I/O supply output signal. The I/O supply output signal has a low voltage value when the I/O supply voltage of the chip is below a medium voltage level and the I/O supply output signal having a high voltage value when the I/O supply voltage of the chip is above the medium voltage level. The medium voltage is above a threshold voltage of the transistor of the I/O circuit and below the high voltage value. The circuit uses the I/O supply output signal to provide a reference voltage as input to the transistor of the I/O circuit.Type: GrantFiled: August 31, 2022Date of Patent: August 27, 2024Assignee: Synopsys, Inc.Inventors: Kailash Kumar, Prateek Singh, Akhil Thotli
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Publication number: 20240273126Abstract: A method may receive a text string of an utterance. A method may tokenize the utterance into a plurality of tokens. A method may transform the plurality of tokens into a plurality of feature vectors. A method may assign an entity label to each of the plurality of feature vectors. A method may resolve each feature vector of the plurality of feature vectors to a corresponding standardized value of a database query language.Type: ApplicationFiled: February 14, 2023Publication date: August 15, 2024Inventors: Hanoz BHATHENA, Prateek SINGH, Aviral JOSHI