Patents by Inventor Prathiba Kumar

Prathiba Kumar has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10353708
    Abstract: Systems, apparatuses, and methods for utilizing efficient vectorization techniques for operands in non-sequential memory locations are disclosed. A system includes a vector processing unit (VPU) and one or more memory devices. In response to determining that a plurality of vector operands are stored in non-sequential memory locations, the VPU performs a plurality of vector load operations to load the plurality of vector operands into a plurality of vector registers. Next, the VPU performs a shuffle operation to consolidate the plurality of vector operands from the plurality of vector registers into a single vector register. Then, the VPU performs a vector operation on the vector operands stored in the single vector register. The VPU can also perform a vector store operation by permuting and storing a plurality of vector operands in appropriate locations within multiple vector registers and then storing the vector registers to locations in memory using a mask.
    Type: Grant
    Filed: September 23, 2016
    Date of Patent: July 16, 2019
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Anupama Rajesh Rasale, Dibyendu Das, Ashutosh Nema, Md Asghar Ahmad Shahid, Prathiba Kumar
  • Publication number: 20180088948
    Abstract: Systems, apparatuses, and methods for utilizing efficient vectorization techniques for operands in non-sequential memory locations are disclosed. A system includes a vector processing unit (VPU) and one or more memory devices. In response to determining that a plurality of vector operands are stored in non-sequential memory locations, the VPU performs a plurality of vector load operations to load the plurality of vector operands into a plurality of vector registers. Next, the VPU performs a shuffle operation to consolidate the plurality of vector operands from the plurality of vector registers into a single vector register. Then, the VPU performs a vector operation on the vector operands stored in the single vector register. The VPU can also perform a vector store operation by permuting and storing a plurality of vector operands in appropriate locations within multiple vector registers and then storing the vector registers to locations in memory using a mask.
    Type: Application
    Filed: September 23, 2016
    Publication date: March 29, 2018
    Inventors: Anupama Rajesh Rasale, Dibyendu Das, Ashutosh Nema, Md Asghar Ahmad Shahid, Prathiba Kumar
  • Patent number: 9921836
    Abstract: Branch sequences for branch prediction performance test are generated by performing the following steps: (i) generating a branch node graph, by a branch node graph generator machine logic set, based, at least in part, upon a set of branch traces of a workload or benchmark code; (ii) generating a first assembly pattern file, for use with a first instruction set architecture (ISA)/microarchitecture set, by an assembly pattern generator machine logic set, based, at least in part, upon the branch node graph so as to mimic the control-flow pattern of the workload or benchmark code; and (iii) running the assembly pattern file on the first ISA/microarchitecture set to obtain first execution results.
    Type: Grant
    Filed: November 2, 2016
    Date of Patent: March 20, 2018
    Assignee: International Business Machines Corporation
    Inventors: Prathiba Kumar, Satish K. Sadasivam
  • Patent number: 9886274
    Abstract: Branch sequences for branch prediction performance test are generated by performing the following steps: (i) generating a branch node graph, by a branch node graph generator machine logic set, based, at least in part, upon a set of branch traces of a workload or benchmark code; (ii) generating a first assembly pattern file, for use with a first instruction set architecture (ISA)/microarchitecture set, by an assembly pattern generator machine logic set, based, at least in part, upon the branch node graph so as to mimic the control-flow pattern of the workload or benchmark code; and (iii) running the assembly pattern file on the first ISA/microarchitecture set to obtain first execution results.
    Type: Grant
    Filed: November 2, 2016
    Date of Patent: February 6, 2018
    Assignee: International Business Machines Corporation
    Inventors: Prathiba Kumar, Satish K. Sadasivam
  • Publication number: 20170060590
    Abstract: Branch sequences for branch prediction performance test are generated by performing the following steps: (i) generating a branch node graph, by a branch node graph generator machine logic set, based, at least in part, upon a set of branch traces of a workload or benchmark code; (ii) generating a first assembly pattern file, for use with a first instruction set architecture (ISA)/microarchitecture set, by an assembly pattern generator machine logic set, based, at least in part, upon the branch node graph so as to mimic the control-flow pattern of the workload or benchmark code; and (iii) running the assembly pattern file on the first ISA/microarchitecture set to obtain first execution results.
    Type: Application
    Filed: November 2, 2016
    Publication date: March 2, 2017
    Inventors: Prathiba Kumar, Satish K. Sadasivam
  • Publication number: 20170046166
    Abstract: Branch sequences for branch prediction performance test are generated by performing the following steps: (i) generating a branch node graph, by a branch node graph generator machine logic set, based, at least in part, upon a set of branch traces of a workload or benchmark code; (ii) generating a first assembly pattern file, for use with a first instruction set architecture (ISA)/microarchitecture set, by an assembly pattern generator machine logic set, based, at least in part, upon the branch node graph so as to mimic the control-flow pattern of the workload or benchmark code; and (iii) running the assembly pattern file on the first ISA/microarchitecture set to obtain first execution results.
    Type: Application
    Filed: November 2, 2016
    Publication date: February 16, 2017
    Inventors: Prathiba Kumar, Satish K. Sadasivam
  • Publication number: 20170031684
    Abstract: Branch sequences for branch prediction performance test are generated by performing the following steps: (i) generating a branch node graph, by a branch node graph generator machine logic set, based, at least in part, upon a set of branch traces of a workload or benchmark code; (ii) generating a first assembly pattern file, for use with a first instruction set architecture (ISA)/microarchitecture set, by an assembly pattern generator machine logic set, based, at least in part, upon the branch node graph so as to mimic the control-flow pattern of the workload or benchmark code; and (iii) running the assembly pattern file on the first ISA/microarchitecture set to obtain first execution results.
    Type: Application
    Filed: October 14, 2016
    Publication date: February 2, 2017
    Inventors: Prathiba Kumar, Satish K. Sadasivam
  • Patent number: 9542183
    Abstract: Branch sequences for branch prediction performance test are generated by performing the following steps: (i) generating a branch node graph, by a branch node graph generator machine logic set, based, at least in part, upon a set of branch traces of a workload or benchmark code; (ii) generating a first assembly pattern file, for use with a first instruction set architecture (ISA)/microarchitecture set, by an assembly pattern generator machine logic set, based, at least in part, upon the branch node graph so as to mimic the control-flow pattern of the workload or benchmark code; and (iii) running the assembly pattern file on the first ISA/microarchitecture set to obtain first execution results.
    Type: Grant
    Filed: March 4, 2016
    Date of Patent: January 10, 2017
    Assignee: International Business Machines Corporation
    Inventors: Prathiba Kumar, Satish K. Sadasivam
  • Patent number: 9519481
    Abstract: Branch sequences for branch prediction performance test are generated by performing the following steps: (i) generating a branch node graph, by a branch node graph generator machine logic set, based, at least in part, upon a set of branch traces of a workload or benchmark code; (ii) generating a first assembly pattern file, for use with a first instruction set architecture (ISA)/microarchitecture set, by an assembly pattern generator machine logic set, based, at least in part, upon the branch node graph so as to mimic the control-flow pattern of the workload or benchmark code; and (iii) running the assembly pattern file on the first ISA/microarchitecture set to obtain first execution results.
    Type: Grant
    Filed: June 27, 2014
    Date of Patent: December 13, 2016
    Assignee: International Business Machines Corporation
    Inventors: Prathiba Kumar, Satish K. Sadasivam
  • Publication number: 20160170750
    Abstract: Branch sequences for branch prediction performance test are generated by performing the following steps: (i) generating a branch node graph, by a branch node graph generator machine logic set, based, at least in part, upon a set of branch traces of a workload or benchmark code; (ii) generating a first assembly pattern file, for use with a first instruction set architecture (ISA)/microarchitecture set, by an assembly pattern generator machine logic set, based, at least in part, upon the branch node graph so as to mimic the control-flow pattern of the workload or benchmark code; and (iii) running the assembly pattern file on the first ISA/microarchitecture set to obtain first execution results.
    Type: Application
    Filed: March 4, 2016
    Publication date: June 16, 2016
    Inventors: Prathiba Kumar, Satish K. Sadasivam
  • Publication number: 20150378728
    Abstract: Branch sequences for branch prediction performance test are generated by performing the following steps: (i) generating a branch node graph, by a branch node graph generator machine logic set, based, at least in part, upon a set of branch traces of a workload or benchmark code; (ii) generating a first assembly pattern file, for use with a first instruction set architecture (ISA)/microarchitecture set, by an assembly pattern generator machine logic set, based, at least in part, upon the branch node graph so as to mimic the control-flow pattern of the workload or benchmark code; and (iii) running the assembly pattern file on the first ISA/microarchitecture set to obtain first execution results.
    Type: Application
    Filed: June 27, 2014
    Publication date: December 31, 2015
    Inventors: Prathiba Kumar, Satish K. Sadasivam
  • Patent number: 9158640
    Abstract: A mechanism is provided for context-aware irritation of a micro-processor. At each executed phase in a set of phases of a test case being executed on a set of micro-processors, a determination is made of a set of characteristics associated with the given executed phase of the test case. Based on the set of determined set of characteristics associated with the given executed phase, a determination is made of an irritation to be executed alongside the given executed phase of the test case. The determined irritation is then executed alongside the given executed phase of the test case.
    Type: Grant
    Filed: November 1, 2013
    Date of Patent: October 13, 2015
    Assignee: International Business Machines Corporation
    Inventors: Sangram Alapati, Prathiba Kumar, Varun Mallikarjunan, Satish K. Sadasivam
  • Patent number: 9129057
    Abstract: The present disclosure includes, but is not limited to, a method, system and computer-usable medium for improving performance measurement by analyzing the various events in a multiplexing counting mode and configuring the sampling time accordingly to more effectively performing the sampling. In certain embodiments, when groups of operations are identified for sampling, the present disclosure generates a time sampling table for these groups of operations. The time sampling table is dynamically altered during the runtime of the application to alter the sampling interval of each group. The sampling interval of each group can be increased or decreased based on a threshold of occurrence of the event. This disclosure provides more accurate performance measurement of important events and facilitates a determination of how important events impact application performance.
    Type: Grant
    Filed: May 1, 2012
    Date of Patent: September 8, 2015
    Assignee: International Business Machines Corporation
    Inventors: Satish K. Sadasivam, Prathiba Kumar, Rajan Ravindran, Sangram Alapati
  • Patent number: 9032375
    Abstract: A computer program product for identifying bottlenecks includes a computer readable storage medium with stored computer readable program instructions. The computer readable program instructions, when executed, provide a data collector module, a mapper module, and an analyzer module that are collectively configured to read mapped data and configuration files, and identify, based upon the mapped data and the configuration files, an undesirable bottleneck condition that causes a computer program to run inefficiently. A method includes reading a configuration file that includes data regarding processor components, and collecting data from hardware activity counters based upon the configuration file.
    Type: Grant
    Filed: April 27, 2011
    Date of Patent: May 12, 2015
    Assignee: International Business Machines Corporation
    Inventors: Prathiba Kumar, Rajan Ravindran, Satish K. Sadasivam, Madhavi G. Valluri
  • Publication number: 20150127984
    Abstract: A mechanism is provided for context-aware irritation of a micro-processor. At each executed phase in a set of phases of a test case being executed on a set of micro-processors, a determination is made of a set of characteristics associated with the given executed phase of the test case. Based on the set of determined set of characteristics associated with the given executed phase, a determination is made of an irritation to be executed alongside the given executed phase of the test case. The determined irritation is then executed alongside the given executed phase of the test case.
    Type: Application
    Filed: November 1, 2013
    Publication date: May 7, 2015
    Applicant: International Business Machines Corporation
    Inventors: Sangram Alapati, Prathiba Kumar, Varun Mallikarjunan, Satish K. Sadasivam
  • Patent number: 9021281
    Abstract: A mechanism is provided for run-time task-level dynamic energy management. An instruction address for a first instruction of the application is mapped to a portion of application code in the application in response to an application being marked for energy management. A monitoring of the hardware resource activities is done for the portion of the application code. A level of energy management is then implemented for the portion of the application code based on a value of the tick indicator, resource activities, and an intensity indicator.
    Type: Grant
    Filed: November 12, 2013
    Date of Patent: April 28, 2015
    Assignee: International Business Machines Corporation
    Inventors: Sangram Alapati, Amit Dugar, Prathiba Kumar, Satish K. Sadasivam
  • Patent number: 8930760
    Abstract: A mechanism is provided for effectively validating cache coherency within a processor. For each node in a set of nodes, responsive to a node in a set of nodes being a controlling node, at least one action is performed on each controlled node mapped to the controlling node. After performing the at least one action on each controlled node mapped to the controlling node or responsive to the node failing to be a controlling node, a self-modifying branch test pattern is executed based on the selected execution pattern in the condition register through the set of nodes. Responsive to the self-modifying branch test pattern ending, values output from the execution unit during execution of the self-modifying branch test pattern are compared to a set of expected results. Responsive to a match of the comparison for the execution patterns in the set of execution patterns, the execution unit is validated.
    Type: Grant
    Filed: December 17, 2012
    Date of Patent: January 6, 2015
    Assignee: International Business Machines Corporation
    Inventors: Sangram Alapati, Prathiba Kumar, Varun Mallikarjunan, Satish K. Sadasivam
  • Patent number: 8914515
    Abstract: A system, and computer program product for cloud optimization using workload analysis are provided in the illustrative embodiments. An architecture of a workload received for execution in a cloud computing environment is identified. The cloud computing environment includes a set of cloud computing resources. A section of the workload is identified and marked for static analysis. Static analysis is performed on the section to determine a characteristic of the workload. A subset of the set of cloud computing resources is selected such that a cloud computing resource in the subset is available for allocating to the workload and has a characteristic that matches the characteristic of the workload as determined from the static analysis. The subset of cloud computing resources is suggested to a job scheduler for scheduling the workload for execution.
    Type: Grant
    Filed: October 28, 2011
    Date of Patent: December 16, 2014
    Assignee: International Business Machines Corporation
    Inventors: Sangram Alapati, Prathiba Kumar, Gowri Shankar Palani, Rajan Ravindran, Satish Kumar Sadasivam
  • Patent number: 8904208
    Abstract: A mechanism is provided for run-time task-level dynamic energy management. An instruction address for a first instruction of the application is mapped to a portion of application code in the application in response to an application being marked for energy management. A monitoring of the hardware resource activities is done for the portion of the application code. A level of energy management is then implemented for the portion of the application code based on a value of the tick indicator, resource activities, and an intensity indicator.
    Type: Grant
    Filed: November 4, 2011
    Date of Patent: December 2, 2014
    Assignee: International Business Machines Corporation
    Inventors: Sangram Alapati, Amit Dugar, Prathiba Kumar, Satish K. Sadasivam
  • Patent number: 8892949
    Abstract: A mechanism is provided for effectively validating execution units within a processor. A branch test pattern is generated for execution by an execution unit that is under validation testing. An execution pattern is selected from a set of execution patterns thereby forming a selected execution pattern. The selected execution pattern is loaded into a condition register. The branch test pattern is executed by an execution unit based on the selected execution pattern in the condition register. Responsive to the branch test pattern ending, values output from the execution unit during execution of the branch test pattern are compared to a set of expected results. Responsive to a match of the comparison, the process is repeated for each execution pattern in the set of execution patterns. Responsive to a match of the comparison for the execution patterns in the set of execution patterns, the execution unit is validated.
    Type: Grant
    Filed: November 1, 2013
    Date of Patent: November 18, 2014
    Assignee: International Business Machines Corporation
    Inventors: Sangram Alapati, Prathiba Kumar, Varun Mallikarjunan, Satish K. Sadasivam