Patents by Inventor Prathiba Kumar
Prathiba Kumar has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 8892949Abstract: A mechanism is provided for effectively validating execution units within a processor. A branch test pattern is generated for execution by an execution unit that is under validation testing. An execution pattern is selected from a set of execution patterns thereby forming a selected execution pattern. The selected execution pattern is loaded into a condition register. The branch test pattern is executed by an execution unit based on the selected execution pattern in the condition register. Responsive to the branch test pattern ending, values output from the execution unit during execution of the branch test pattern are compared to a set of expected results. Responsive to a match of the comparison, the process is repeated for each execution pattern in the set of execution patterns. Responsive to a match of the comparison for the execution patterns in the set of execution patterns, the execution unit is validated.Type: GrantFiled: November 1, 2013Date of Patent: November 18, 2014Assignee: International Business Machines CorporationInventors: Sangram Alapati, Prathiba Kumar, Varun Mallikarjunan, Satish K. Sadasivam
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Patent number: 8850266Abstract: A mechanism is provided for effectively validating execution units within a processor. A branch test pattern is generated for execution by an execution unit that is under validation testing. An execution pattern is selected from a set of execution patterns thereby forming a selected execution pattern. The selected execution pattern is loaded into a condition register. The branch test pattern is executed by an execution unit based on the selected execution pattern in the condition register. Responsive to the branch test pattern ending, values output from the execution unit during execution of the branch test pattern are compared to a set of expected results. Responsive to a match of the comparison, the process is repeated for each execution pattern in the set of execution patterns. Responsive to a match of the comparison for the execution patterns in the set of execution patterns, the execution unit is validated.Type: GrantFiled: June 14, 2011Date of Patent: September 30, 2014Assignee: International Business Machines CorporationInventors: Sangram Alapati, Prathiba Kumar, Varun Mallikarjunan, Satish K. Sadasivam
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Patent number: 8838801Abstract: A method for cloud optimization using workload analysis is provided in the illustrative embodiments. An architecture of a workload received for execution in a cloud computing environment is identified. The cloud computing environment includes a set of cloud computing resources. A section of the workload is identified and marked for static analysis. Static analysis is performed on the section to determine a characteristic of the workload. A subset of the set of cloud computing resources is selected such that a cloud computing resource in the subset is available for allocating to the workload and has a characteristic that matches the characteristic of the workload as determined from the static analysis. The subset of cloud computing resources is suggested to a job scheduler for scheduling the workload for execution.Type: GrantFiled: July 16, 2012Date of Patent: September 16, 2014Assignee: International Business Machines CorporationInventors: Sangram Alapati, Prathiba Kumar, Gowri Palani, Rajan Ravindran, Satish Kumar Sadasivam
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Publication number: 20140173222Abstract: A mechanism is provided for effectively validating cache coherency within a processor. For each node in a set of nodes, responsive to a node in a set of nodes being a controlling node, at least one action is performed on each controlled node mapped to the controlling node. After performing the at least one action on each controlled node mapped to the controlling node or responsive to the node failing to be a controlling node, a self-modifying branch test pattern is executed based on the selected execution pattern in the condition register through the set of nodes. Responsive to the self-modifying branch test pattern ending, values output from the execution unit during execution of the self-modifying branch test pattern are compared to a set of expected results. Responsive to a match of the comparison for the execution patterns in the set of execution patterns, the execution unit is validated.Type: ApplicationFiled: December 17, 2012Publication date: June 19, 2014Applicant: International Business Machines CorporationInventors: Sangram Alapati, Prathiba Kumar, Varun Mallikarjunan, Satish K. Sadasivam
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Publication number: 20140075219Abstract: A mechanism is provided for run-time task-level dynamic energy management. An instruction address for a first instruction of the application is mapped to a portion of application code in the application in response to an application being marked for energy management. A monitoring of the hardware resource activities is done for the portion of the application code. A level of energy management is then implemented for the portion of the application code based on a value of the tick indicator, resource activities, and an intensity indicator.Type: ApplicationFiled: November 12, 2013Publication date: March 13, 2014Applicant: International Business Machines CorporationInventors: Sangram Alapati, Amit Dugar, Prathiba Kumar, Satish K. Sadasivam
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Patent number: 8667255Abstract: A post-silicon testing apparatus, method, and computer program product provide for runtime coverage measurement methodology to measure the architectural events in hardware. Measurement of all architectural events discernable from the instructions and architectural state changes are tracked and recorded. A mechanism to ensure capturing of maskable events is also provided. A feedback driven test-generation approach is enabled by the runtime coverage measurement. The runtime coverage measurement system presents a live view of the comprehensive architectural event coverage to the user/tester. The methodology can be implemented on an operating system environment and also as a standalone/bare-metal tool.Type: GrantFiled: September 30, 2010Date of Patent: March 4, 2014Assignee: International Business Machines CorporationInventors: Sangram Alapati, Jayakumar N Sankarannair, Varun Mallikarjunan, Prathiba Kumar, Satish Kumar Sadasivam
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Publication number: 20140059383Abstract: A mechanism is provided for effectively validating execution units within a processor. A branch test pattern is generated for execution by an execution unit that is under validation testing. An execution pattern is selected from a set of execution patterns thereby forming a selected execution pattern. The selected execution pattern is loaded into a condition register. The branch test pattern is executed by an execution unit based on the selected execution pattern in the condition register. Responsive to the branch test pattern ending, values output from the execution unit during execution of the branch test pattern are compared to a set of expected results. Responsive to a match of the comparison, the process is repeated for each execution pattern in the set of execution patterns. Responsive to a match of the comparison for the execution patterns in the set of execution patterns, the execution unit is validated.Type: ApplicationFiled: November 1, 2013Publication date: February 27, 2014Applicant: International Business Machines CorporationInventors: Sangram Alapati, Prathiba Kumar, Varun Mallikarjunan, Satish K. Sadasivam
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Patent number: 8607243Abstract: A method for dynamic optimization of thread assignments for application workloads in an simultaneous multi-threading (SMT) computing environment includes monitoring and periodically recording an operational status of different processor cores each supporting a number of threads of the thread pool of the SMT computing environment and also operational characteristics of different workloads of a computing application executing in the SMT computing environment. The method further can include identifying by way of the recorded operational characteristics a particular one of the workloads demonstrating a threshold level of activity. Finally, the method can include matching a recorded operational characteristic of the particular one of the workloads to a recorded status of a processor core best able amongst the different processor cores to host execution in one or more threads of the particular one of the workloads and directing the matched processor core to host execution of the particular one of the workloads.Type: GrantFiled: September 20, 2011Date of Patent: December 10, 2013Assignee: International Business Machines CorporationInventors: Prathiba Kumar, Varun Mallikarjunan, Rajan Ravindran, Satish Kumar Sadasivam
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Publication number: 20130297258Abstract: The present disclosure includes, but is not limited to, a method, system and computer-usable medium for improving performance measurement by analyzing the various events in a multiplexing counting mode and configuring the sampling time accordingly to more effectively performing the sampling. In certain embodiments, when groups of operations are identified for sampling, the present disclosure generates a time sampling table for these groups of operations. The time sampling table is dynamically altered during the runtime of the application to alter the sampling interval of each group. The sampling interval of each group can be increased or decreased based on a threshold of occurrence of the event. This disclosure provides more accurate performance measurement of important events and facilitates a determination of how important events impact application performance.Type: ApplicationFiled: May 1, 2012Publication date: November 7, 2013Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Satish K. Sadasivam, Prathiba Kumar, Rajan Ravindran, Sangram Alapati
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Publication number: 20130117588Abstract: A mechanism is provided for run-time task-level dynamic energy management. An instruction address for a first instruction of the application is mapped to a portion of application code in the application in response to an application being marked for energy management. A monitoring of the hardware resource activities is done for the portion of the application code. A level of energy management is then implemented for the portion of the application code based on a value of the tick indicator, resource activities, and an intensity indicator.Type: ApplicationFiled: November 4, 2011Publication date: May 9, 2013Applicant: International Business Machines CorporationInventors: Sangram Alapati, Amit Dugar, Prathiba Kumar, Satish K. Sadasivam
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Publication number: 20130111035Abstract: A method for cloud optimization using workload analysis is provided in the illustrative embodiments. An architecture of a workload received for execution in a cloud computing environment is identified. The cloud computing environment includes a set of cloud computing resources. A section of the workload is identified and marked for static analysis. Static analysis is performed on the section to determine a characteristic of the workload. A subset of the set of cloud computing resources is selected such that a cloud computing resource in the subset is available for allocating to the workload and has a characteristic that matches the characteristic of the workload as determined from the static analysis. The subset of cloud computing resources is suggested to a job scheduler for scheduling the workload for execution.Type: ApplicationFiled: July 16, 2012Publication date: May 2, 2013Inventors: Sangram Alapati, Prathiba Kumar, Gowri Palani, Rajan Ravindran, Satish Kumar Sadasivam
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Publication number: 20130111032Abstract: A method, system, and computer program product for cloud optimization using workload analysis are provided in the illustrative embodiments. An architecture of a workload received for execution in a cloud computing environment is identified. The cloud computing environment includes a set of cloud computing resources. A section of the workload is identified and marked for static analysis. Static analysis is performed on the section to determine a characteristic of the workload. A subset of the set of cloud computing resources is selected such that a cloud competing resource in the subset is available for allocating to the workload and has a characteristic that matches the characteristic of the workload as determined from the static analysis. The subset of cloud computing resources is suggested to a job scheduler for scheduling the workload for execution.Type: ApplicationFiled: October 28, 2011Publication date: May 2, 2013Applicant: International Business Machines CorporationInventors: Sangram Alapati, Prathiba Kumar, Gowri Shankar Palani, Rajan Ravindran, Satish Kumar Sadasivam
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Publication number: 20130074090Abstract: A method for dynamic optimization of thread assignments for application workloads in an simultaneous multi-threading (SMT) computing environment includes monitoring and periodically recording an operational status of different processor cores each supporting a number of threads of the thread pool of the SMT computing environment and also operational characteristics of different workloads of a computing application executing in the SMT computing environment. The method further can include identifying by way of the recorded operational characteristics a particular one of the workloads demonstrating a threshold level of activity. Finally, the method can include matching a recorded operational characteristic of the particular one of the workloads to a recorded status of a processor core best able amongst the different processor cores to host execution in one or more threads of the particular one of the workloads and directing the matched processor core to host execution of the particular one of the workloads.Type: ApplicationFiled: September 20, 2011Publication date: March 21, 2013Applicant: International Business Machines Corporation New Orchard RoadInventors: Prathiba Kumar, Varun Mallikarjunan, Rajan Ravindran, Satish Kumar Sadasivam
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Publication number: 20130074084Abstract: A method for dynamic optimization of thread assignments for application workloads in an simultaneous multi-threading (SMT) computing environment includes monitoring and periodically recording an operational status of different processor cores each supporting a number of threads of the thread pool of the SMT computing environment and also operational characteristics of different workloads of a computing application executing in the SMT computing environment. The method further can include identifying by way of the recorded operational characteristics a particular one of the workloads demonstrating a threshold level of activity. Finally, the method can include matching a recorded operational characteristic of the particular one of the workloads to a recorded status of a processor core best able amongst the different processor cores to host execution in one or more threads of the particular one of the workloads and directing the matched processor core to host execution of the particular one of the workloads.Type: ApplicationFiled: June 15, 2012Publication date: March 21, 2013Applicant: International Business Machines CorporationInventors: Prathiba Kumar, Varun MALLIKARJUNAN, Rajan RAVINDRAN, Satish Kumar SADASIVAM
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Publication number: 20120324208Abstract: A mechanism is provided for effectively validating execution units within a processor. A branch test pattern is generated for execution by an execution unit that is under validation testing. An execution pattern is selected from a set of execution patterns thereby forming a selected execution pattern. The selected execution pattern is loaded into a condition register. The branch test pattern is executed by an execution unit based on the selected execution pattern in the condition register. Responsive to the branch test pattern ending, values output from the execution unit during execution of the branch test pattern are compared to a set of expected results. Responsive to a match of the comparison, the process is repeated for each execution pattern in the set of execution patterns. Responsive to a match of the comparison for the execution patterns in the set of execution patterns, the execution unit is validated.Type: ApplicationFiled: June 14, 2011Publication date: December 20, 2012Applicant: International Business Machines CorporationInventors: Sangram Alapati, Prathiba Kumar, Varun Mallikarjunan, Satish K. Sadasivam
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Publication number: 20120278594Abstract: A computer program product for identifying bottlenecks includes a computer readable storage medium with stored computer readable program instructions. The computer readable program instructions, when executed, provide a data collector module, a mapper module, and an analyzer module that are collectively configured to read mapped data and configuration files, and identify, based upon the mapped data and the configuration files, an undesirable bottleneck condition that causes a computer program to run inefficiently. A method includes reading a configuration file that includes data regarding processor components, and collecting data from hardware activity counters based upon the configuration file.Type: ApplicationFiled: April 27, 2011Publication date: November 1, 2012Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Prathiba Kumar, Rajan Ravindran, Satish K. Sadasivam, Madhavi G. Valluri
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Publication number: 20120084028Abstract: A method, a system and a computer program product for determining power consumption levels for granular segments of program code in a data processing system. A power profiling utility (PPU) utilizes/comprises a power monitoring module, a power profiler module, a performance profiler and a power modeling component which enables PPU to efficiently characterize power consumption of various types of applications. The PPU uses a power measurement device to obtain power consumption measurements corresponding to execution of a first code segment. Additionally, the PPU identifies information about program characteristics of granular code segments within the first code segment. The PPU then determines total power consumption for execution of the first code segment from an aggregation of power consumption measurements corresponding to all iterations of the first code segment.Type: ApplicationFiled: September 30, 2010Publication date: April 5, 2012Applicant: IBM CORPORATIONInventors: Prathiba Kumar, Satish Kumar Sadasivam, Giri M. Prabhakar
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Publication number: 20120084538Abstract: A post-silicon testing apparatus, method, and computer program product provide for runtime coverage measurement methodology to measure the architectural events in hardware. Measurement of all architectural events discernable from the instructions and architectural state changes are tracked and recorded. A mechanism to ensure capturing of maskable events is also provided. A feedback driven test-generation approach is enabled by the runtime coverage measurement. The runtime coverage measurement system presents a live view of the comprehensive architectural event coverage to the user/tester. The methodology can be implemented on an operating system environment and also as a standalone/bare-metal tool.Type: ApplicationFiled: September 30, 2010Publication date: April 5, 2012Applicant: IBM CORPORATIONInventors: Sangram Alapati, Jayakumar N. Sankarannair, Varun Mallikarjunan, Prathiba Kumar, Satish Kumar Sadasivam
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Patent number: 8140901Abstract: A method for testing processors is disclosed. The method includes generating a plurality of pools, where each pool includes a test program that includes a plurality of test cases, and setting a flag for each of the plurality of pools indicating that the pool is ready to be executed. Each processor performs a pool execution cycle a predetermined number of times. The pool execution cycle includes selecting a pool that is ready to be executed and unsetting the flag for the selected pool, performing an execution cycle of the test program included in the selected pool, and setting the flag indicating that the pool is ready to be executed upon completion of the execution cycle of the test program. The execution cycle of the test program includes regenerating a test case to create a new case that is flagged as the next test case for execution in the execution cycle.Type: GrantFiled: November 30, 2009Date of Patent: March 20, 2012Assignee: International Business Machines CorporationInventors: Prathiba Kumar, Satish Kumar Sadasivam, Srinivasan Subramanian
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Publication number: 20110131452Abstract: A method for testing processors is disclosed. The method includes generating a plurality of pools, where each pool includes a test program that includes a plurality of test cases, and setting a flag for each of the plurality of pools indicating that the pool is ready to be executed. Each processor performs a pool execution cycle a predetermined number of times. The pool execution cycle includes selecting a pool that is ready to be executed and unsetting the flag for the selected pool, performing an execution cycle of the test program included in the selected pool, and setting the flag indicating that the pool is ready to be executed upon completion of the execution cycle of the test program. The execution cycle of the test program includes regenerating a test case to create a new case that is flagged as the next test case for execution in the execution cycle.Type: ApplicationFiled: November 30, 2009Publication date: June 2, 2011Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Prathiba Kumar, Satish Kumar Sadasivam, Srinivasan Subramanian