Abstract: A multi-processor system includes first and second central processing units (CPUs) connected by a processor interconnect, a single baseboard management controller for managing operation of the first and second CPUs, wherein the first and second CPUs are operable as a single unified node, and a single keyboard, video and mouse connection, wherein the single keyboard, video and mouse connection includes a video controller and a USB controller. The multi-processor system may further comprise a multiplexer connected to the video controller and the USB controller, wherein the multiplexer has a selectable PCIe connection to either the first central processing unit or the second central processing unit. Program instructions may be executable by the baseboard management controller to send a selection signal to the multiplexer.

Abstract: A method for automatically switching input/output (“I/O”) between partitioned systems based on power usage includes monitoring power usage for each of two or more systems, selecting a system of the two or more systems in response to power usage of the of the system reaching a power usage threshold, and switching an input of an I/O switch to send data for display of one or more elements of the selected system to an electronic display.

Abstract: A method for automatically switching input/output (“I/O”) between partitioned systems based on system events includes monitoring a system state for each of two or more systems sharing an electronic display, where each of the two or more systems includes a processor executing an instance of an operating system, selecting a system of the two or more systems sharing the electronic display in response to determining that a change has occurred in the system state of the of the selected system, and switching an input of an I/O switch to send data for display of one or more elements of the selected system to the electronic display.

Abstract: A method for automatically switching input/output (“I/O”) between partitioned systems based on system events includes monitoring a system state for each of two or more systems sharing an electronic display, where each of the two or more systems includes a processor executing an instance of an operating system, selecting a system of the two or more systems sharing the electronic display in response to determining that a change has occurred in the system state of the of the selected system, and switching an input of an I/O switch to send data for display of one or more elements of the selected system to the electronic display.

Abstract: A method for automatically switching between partition configurations at a scheduled time period includes storing, at a service processor, a plurality of partition configurations for a computing system, the plurality of partition configurations allocating hardware resources of the computing system. The method includes associating a configuration schedule with the plurality of partition configurations, where each of the plurality of partition configurations is associated with a scheduled time period, and booting the computing system to a particular partition configuration at a particular scheduled time period corresponding to the particular partition configuration.

Abstract: A partitionable multi-processor system includes a first plurality of components of the multi-processor system forming a first partitioned node that is operable as a first independent node, a second plurality of components of the multi-processor system forming a second partitioned node that is operable as a second independent node and a system controller that is configured to selectively and independently control separate power, clock, and/or reset signals to the first plurality of components forming the first partitioned node and the second plurality of components forming the second partitioned node in response to receiving a first partitioning mode instruction from a baseboard management controller (BMC) that identifies a partitioned state and configured to selectively control the separate power, clock, and/or reset signals to the first and second pluralities of components in a unified manner in response to receiving a second partitioning mode instruction from the BMC that identifies a unified state.

Abstract: A baseboard management controller in a multi-processor system may perform operations including: identifying a partitioning mode (partitioned state or unified state) to implement on the multi-processor system having first and second central processing units (CPUs) located on a single motherboard; accessing, in response to the partitioned state, a first partitioned node configuration (P1C) for a first partitioned node (P1) and a second partitioned node configuration (P2C) for a second partitioned node (P2), wherein P1C identifies a first firmware interface level (F1L) and a first operating system to be used by P1, and wherein P2C identifies a second firmware interface level (F2L) and a second operating system to be used by P2; and causing the first CPU to load a first firmware interface having the identified F1L identified in the P1C and causing the second CPU to load a second firmware interface having the F2L identified in the P2C.

Abstract: A baseboard management controller in a multi-processor system may perform operations including: causing, during a first time period, the system to operate in a partitioned state with a first partitioned node including a first subset of components of the system and a second partitioned node including a second subset of components of the system, wherein the first and second partitioned nodes are independently operable nodes having their own operating systems, and wherein the first partitioned node boots from a first boot drive that is included in the first subset; causing, during a second time period, the system to operate in a unified state with a single unified node including components from both the first and second subsets of components, wherein the single unified node has its own operating system; and causing the first boot drive to be inaccessible to the second partitioned node and the single unified node.

Abstract: A partitionable multi-processor system includes a first plurality of components of the multi-processor system forming a first partitioned node that is operable as a first independent node, a second plurality of components of the multi-processor system forming a second partitioned node that is operable as a second independent node and a system controller that is configured to selectively and independently control separate power, clock, and/or reset signals to the first plurality of components forming the first partitioned node and the second plurality of components forming the second partitioned node in response to receiving a first partitioning mode instruction from a baseboard management controller (BMC) that identifies a partitioned state and configured to selectively control the separate power, clock, and/or reset signals to the first and second pluralities of components in a unified manner in response to receiving a second partitioning mode instruction from the BMC that identifies a unified state.

Abstract: A baseboard management controller in a partitionable multi-processor system may perform operations including receiving a plurality of event notifications from the partitionable multi-processor system including one or more event notifications from a first partitioned node including a first subset of hardware devices of the multi-processor system and one or more event notifications from a second partitioned node including a second subset of the hardware devices of the multi-processor system, wherein each event notification identifies an event and a specific one of the hardware devices that experienced the event. The operations may further include receiving a request for an event log for the first partitioned node and providing the requested event log for the first partitioned node including only those event notifications that identify a hardware device that is included in the first partitioned node.

Abstract: Embodiments provide a method and a computer program product providing program instructions executable by a processor of a baseboard management controller in a multi-processor system to cause the processor to perform various operations. The operations include identifying a number of cores present in each of a plurality of central processing units in the multi-processor system, initiating operation of the multi-processor system as a single unified node in response to each of the plurality of central processing units having an equal number of cores, and initiating partitioning of the multi-processor system into first and second independent partitioned nodes in response to a first set of one or more of the central processing units each having a first number of cores and a second set of one or more of the central processing units each having a second number of cores that is different than the first number of cores.

Abstract: A baseboard management controller in a multi-processor system may perform operations including: causing, during a first time period, the system to operate in a partitioned state with a first partitioned node including a first subset of components of the system and a second partitioned node including a second subset of components of the system, wherein the first and second partitioned nodes are independently operable nodes having their own operating systems, and wherein the first partitioned node boots from a first boot drive that is included in the first subset; causing, during a second time period, the system to operate in a unified state with a single unified node including components from both the first and second subsets of components, wherein the single unified node has its own operating system; and causing the first boot drive to be inaccessible to the second partitioned node and the single unified node.

Abstract: A baseboard management controller in a multi-processor system may perform operations including: identifying a partitioning mode (partitioned state or unified state) to implement on the multi-processor system having first and second central processing units (CPUs) located on a single motherboard; accessing, in response to the partitioned state, a first partitioned node configuration (P1C) for a first partitioned node (P1) and a second partitioned node configuration (P2C) for a second partitioned node (P2), wherein P1C identifies a first firmware interface level (F1L) and a first operating system to be used by P1, and wherein P2C identifies a second firmware interface level (F2L) and a second operating system to be used by P2; and causing the first CPU to load a first firmware interface having the identified F1L identified in the P1C and causing the second CPU to load a second firmware interface having the F2L identified in the P2C.

Abstract: A method for automatically switching input/output (“I/O”) between partitioned systems based on power usage includes monitoring power usage for each of two or more systems, selecting a system of the two or more systems in response to power usage of the of the system reaching a power usage threshold, and switching an input of an I/O switch to send data for display of one or more elements of the selected system to an electronic display.

Abstract: A multi-processor system includes first and second central processing units (CPUs) connected by a processor interconnect, a single baseboard management controller for managing operation of the first and second CPUs, wherein the first and second CPUs are operable as a single unified node, and a single keyboard, video and mouse connection, wherein the single keyboard, video and mouse connection includes a video controller and a USB controller. The multi-processor system may further comprise a multiplexer connected to the video controller and the USB controller, wherein the multiplexer has a selectable PCIe connection to either the first central processing unit or the second central processing unit. Program instructions may be executable by the baseboard management controller to send a selection signal to the multiplexer.

Abstract: A computer program product includes a non-volatile computer readable medium and non-transitory program instructions embodied therein, the program instructions being configured to be executable by a processor of a baseboard management controller in a multi-processor system to cause the processor to perform various operations. The operations include initiating disabling of a processor interconnect between first and second central processing units in the multi-processor system and initiating boot of the first central processing unit, wherein the first central processing unit operates in a first partitioned node independent of the second central processing unit.

Abstract: A system includes a partitionable multi-processor motherboard that has multiple central processing units, wherein the multi-processor motherboard may be configured to operate as a single unified node or configured to operate as multiple independent partitioned nodes. The system further comprises a single power button that is accessible to a user, wherein the single power button generates an output signal while being pressed, and an integrated circuit installed on the motherboard and connected to receive the output signal from the power button, wherein the integrated circuit stores a first button press gesture definition associated with selection of a first partitioned node, a second button press gesture definition associated with selection of a second partitioned node, and a third button press gesture definition associated with sequencing power to the selected one of the first or second partitioned nodes.

Abstract: Embodiments provide a method and computer program product including program instructions executable by a baseboard management controller in a multi-processor system to perform various operations. The operations include detecting a number of memory modules connected to each of a plurality of central processing units (CPUs) in the multi-processor system during boot, initiating operation of the multi-processor system as a single unified node in response to each of the CPUs being connected to an equal number of memory modules, and initiating partitioning of the multi-processor system into a first partitioned node and a second partitioned node in response to a first set of one or more of the CPUs each being connected to a first number of memory modules and a second set of one or more of the CPUs each being connected to a second number of memory modules that is different than the first number of memory modules.

Abstract: A control circuit is provided on a printed circuit board to detect the presence of a memory module installed in at least one of a plurality of memory module connectors, wherein installation of the memory module is known to cause impedance to decrease in a segment of a daisy chain memory circuit. The impedance of a first signal conductor of the daisy chain memory circuit is automatically altered to reduce a mismatch in impedance between the first signal conductor and the segment in response to detecting the presence of the memory module in the connector. A metal element is incorporated into the printed circuit board a spaced distance from the first signal conductor, and the control circuit may selectively activate one or more relays to cause the metal element to function as either a floating trace or a ground reference.

Abstract: A control circuit is provided on a printed circuit board to detect the presence of a memory module installed in at least one of a plurality of memory module connectors, wherein installation of the memory module is known to cause impedance to decrease in a segment of a daisy chain memory circuit. The impedance of a first signal conductor of the daisy chain memory circuit is automatically altered to reduce a mismatch in impedance between the first signal conductor and the segment in response to detecting the presence of the memory module in the connector. A metal element is incorporated into the printed circuit board a spaced distance from the first signal conductor, and the control circuit may selectively activate one or more relays to cause the metal element to function as either a floating trace or a ground reference.