Abstract: A current detection system includes an inductor and a detection circuit coupled across the inductor. The inductor is configured to receive an input signal that includes an input current and generate a voltage across the inductor. The current detection circuit includes a sensing network and a transconductance amplifier. The sensing network includes a capacitor and is configured to monitor a voltage across the inductor. The transconductance amplifier is configured to receive a differential voltage indicative of a voltage drop across the capacitor and output a differential output current proportional to the differential voltage.

Abstract: A current detection system includes an inductor and a detection circuit coupled across the inductor. The inductor is configured to receive an input signal that includes an input current and generate a voltage across the inductor. The current detection circuit includes a sensing network and a transconductance amplifier. The sensing network includes a capacitor and is configured to monitor a voltage across the inductor. The transconductance amplifier is configured to receive a differential voltage indicative of a voltage drop across the capacitor and output a differential output current proportional to the differential voltage.

Abstract: A circuit for a multi-phase power regulator including a power stage with a first phase and a second phase, the circuit including phase management circuitry coupled to the first phase and the second phase to control the first phase and the second phase, a first comparator coupled to an output of the multi-phase power regulator to compare a value of the output of the multi-phase power regulator to a first threshold value to produce a first comparison result, and phase shedding circuitry coupled to the first comparator and the phase management circuitry to control the phase management circuitry to activate or deactivate the second phase based at least partially on the first comparison result.

Abstract: A one-time programmable (OTP) circuit. The OTP circuit includes a non-volatile OTP memory disposed on a first circuit die. The OTP memory includes a floating gate terminal. The OTP circuit also includes a cross-coupled latch disposed on the first circuit die and coupled to the OTP memory and volatile memory input circuitry disposed on the first circuit die and coupled to the cross-coupled latch. The volatile memory input circuitry is configured to receive a test value and write the test value into the cross-coupled latch. The OTP circuit is configured to receive a programming command and store the test value in the OTP memory in response to receipt of the programming command.

Abstract: A current detection system includes an inductor and a detection circuit coupled across the inductor. The inductor is configured to receive an input signal that includes an input current and generate a voltage across the inductor. The current detection circuit includes a sensing network and a transconductance amplifier. The sensing network includes a capacitor and is configured to monitor a voltage across the inductor. The transconductance amplifier is configured to receive a differential voltage indicative of a voltage drop across the capacitor and output a differential output current proportional to the differential voltage.

Abstract: A control circuit for a DC-DC converter and a DC-DC converter are disclosed. The control circuit includes an integrator coupled to receive a first reference voltage and a first voltage that includes an output voltage for the DC-DC converter and to provide an integrated error signal. A first comparator is coupled to receive the first reference voltage and the first voltage and to provide a dynamic-integration signal that adjusts the integration time constant of the integrator.

Abstract: A voltage converter includes a high side power transistor coupled to an input voltage node and a low side power transistor coupled to the high side power transistor at a switch node. The switch node is configured to be coupled to an inductor. A slope detector circuit is configured to receive a signal indicative of a current through the inductor. The inductor current is a triangular waveform comprising a ramp-up phase and a ramp-down phase. The slope detector circuit also is configured to generate an output signal encoding when the inductor current is ramping up and when the inductor current is ramping down.

Abstract: A voltage converter circuit includes a high side transistor, a high side driver coupled to a control input of the high side transistor, a low side transistor coupled to the high side transistor at a switch node, and a current steering circuit coupled to the control input of the high side and to the switch node. During transition of the high side transistor to an on state, a current from the high side driver initially divides between the control input of the high side transistor and the current steering circuit, and as a voltage on the switch node increases, less of the current from the high side driver flows through the current steering circuit and more of the current from the high side driver flows to the control input of the high side transistor.

Abstract: In some embodiments, a resistor string digital to analog converter (DAC) comprises a first plurality of resistors disposed in a first column. Each of the first plurality of resistors couples to an output of the first column via one of a first plurality of switches. The DAC also comprises a second plurality of resistors disposed in a second column. Each of the second plurality of resistors couples to an output of the second column via one of a second plurality of switches. The second plurality of resistors is configured to couple in series with the first plurality of resistors. A first row selection signal is to control a first switch of the first plurality of switches and a second switch of the second plurality of switches. The first switch corresponds to a first resistor disposed at a top of the first column, and the second switch corresponds to a second resistor disposed at a bottom of the second column.

Abstract: An integrated circuit (IC) is provided with functional logic having a plurality of internal signal lines and test logic. The test logic has a plurality of inputs coupled to the plurality of internal signal lines and with an output coupled to a first external pin of the integrated circuit. The test logic includes a buffer, and the test logic is configured to selectively couple each of the signals received on the plurality of signal lines either directly or via the buffer to the first external pin of the IC. The test logic may be configured to selectively couple a signal received on a second external pin of the IC either via the buffer to the first external pin of the IC in order to calibrate the buffer.

Abstract: A circuit and method for providing improved load transient response in a DC-DC converter. A DCM modulator is incorporated into the converter controller to generate a DCM enable signal for the driver circuits for the converter. During normal operation, the DCM enable signal will remain in a first state and the driver circuits will operate in a continuous conduction mode. However, upon a load transient, the DCM enable signal will change to a second state and the driver circuits will operate in a discontinuous conduction mode.

Abstract: In a described example, a method includes using a power supply, supplying an output voltage that varies in response to a reference voltage; detecting a voltage ramp in an input reference voltage; generating an offset voltage waveform; adding the offset voltage waveform to the input reference voltage to generate a second reference voltage; and using the second reference voltage, operating the power supply to supply the output voltage.

Abstract: A one-time programmable (OTP) circuit. The OTP circuit includes a non-volatile OTP memory disposed on a first circuit die. The OTP memory includes a floating gate terminal. The OTP circuit also includes a cross-coupled latch disposed on the first circuit die and coupled to the OTP memory and volatile memory input circuitry disposed on the first circuit die and coupled to the cross-coupled latch. The volatile memory input circuitry is configured to receive a test value and write the test value into the cross-coupled latch. The OTP circuit is configured to receive a programming command and store the test value in the OTP memory in response to receipt of the programming command.

Abstract: An integrated circuit (IC) is provided with functional logic having a plurality of internal signal lines and test logic. The test logic has a plurality of inputs coupled to the plurality of internal signal lines and with an output coupled to a first external pin of the integrated circuit. The test logic includes a buffer, and the test logic is configured to selectively couple each of the signals received on the plurality of signal lines either directly or via the buffer to the first external pin of the IC. The test logic is configured to selectively couple a signal received on a second external pin of the IC either via the buffer to the first external pin of the IC in order to calibrate the buffer.

Abstract: An integrated circuit (IC) is provided with functional logic having a plurality of internal signal lines and test logic. The test logic has a plurality of inputs coupled to the plurality of internal signal lines and with an output coupled to a first external pin of the integrated circuit. The test logic includes a buffer, and the test logic is configured to selectively couple each of the signals received on the plurality of signal lines either directly or via the buffer to the first external pin of the IC. The test logic may be configured to selectively couple a signal received on a second external pin of the IC either via the buffer to the first external pin of the IC in order to calibrate the buffer.

Abstract: A circuit and method for providing improved load transient response in a DC-DC converter. A DCM modulator is incorporated into the converter controller to generate a DCM enable signal for the driver circuits for the converter. During normal operation, the DCM enable signal will remain in a first state and the driver circuits will operate in a continuous conduction mode. However, upon a load transient, the DCM enable signal will change to a second state and the driver circuits will operate in a discontinuous conduction mode.

Abstract: A low-impedance output stage which operates from a low voltage power supply. In an embodiment, the output stage contains an operational amplifier and two PMOS transistors used in a feedback configuration resulting in low output impedance. The output stage may also include a capacitor connected between the output terminal of the output stage and the input of the PMOS transistor providing the output, resulting in an overall output impedance which remains low even at higher frequencies, thus enabling use of the output stage to drive capacitive loads without causing resonance.

Abstract: A voltage generation circuit generating a reference voltage using a bandgap reference. A countering circuit is included to adaptively counter for any deviations caused in a bandgap reference voltage such that the reference voltage is independent of fabrication process variations and changes in ambient temperature. In an embodiment, current, proportionate to deviation in absolute value of Vbe from a nominal value, is injected into the emitter-base junction to cause Vbe to equal the nominal value.

Abstract: Reducing the bias voltage level required in a boost amplifier enhancing a gain of amplifier comprising first and second amplification stages. In an embodiment, the booster amplifier circuit contains a first transistor receiving both the bias voltage and the input signal respectively on the gate and source terminal and the drain terminal is coupled to second amplification stage of the high gain amplifier.

Abstract: An amplifier sharing technique in an analog to digital converter (ADC) in which a cascaded combination of a pre-amplifier and main amplifier is used to provide the required amplification for a first stage, and only the main amplifier is used to provide the amplification for the second stage. Switches and capacitors are used in conjunction such that the sampling and feedback capacitors of the first stage are connected across the cascaded combination in a first phase, and sampling and feedback capacitors of the second stage are connected across the main amplifier in a second phase. By appropriate choice of parameter values for various components, the second poles due to the pre-amplifier may be located at the higher frequency ranges obtaining the required unity gain bandwidth (UGB) without Miller compensation and/or additional gain.