Patents by Inventor Preetham M Lobo
Preetham M Lobo has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11789518Abstract: Embodiments relate to a system, program product, and method for mitigating voltage overshoot in one or more cores in a multicore processing device including a plurality of cores. The method includes determining, in real-time, an indication of power consumption within each core of the one or more cores. The method also includes determining, through the indication of power consumption, a voltage overshoot condition in the one or more cores. The method further includes increasing, for the one or more cores, a power demand thereof. The method also includes increasing, subject to the increasing the power demand, power delivery to the one or more cores, thereby at least arresting the rate of increase of the voltage overshoot.Type: GrantFiled: June 22, 2021Date of Patent: October 17, 2023Assignee: International Business Machines CorporationInventors: Pradeep Bhadravati Parashurama, Alper Buyuktosunoglu, Ramon Bertran Monfort, Tobias Webel, Srinivas Bangalore Purushotham, Preetham M. Lobo
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Patent number: 11782683Abstract: A system for variable replacement in a template artificial intelligence (AI) accelerator code. The system includes: at least one memory; at least one processor communicatively coupled to the at least one memory, and configured for computing at least one table of variables from a template AI accelerator code; and an AI accelerator including a plurality of engines, and communicatively coupled to the at least one processor and the at least one memory. The AI accelerator is configured to create a variable replaced AI accelerator code for the plurality of engines of the AI accelerator from the template AI accelerator code by replacing variables in the template AI accelerator code with actual values from the at least one table of variables.Type: GrantFiled: March 24, 2022Date of Patent: October 10, 2023Assignee: International Business Machines CorporationInventors: Cedric Lichtenau, Preetham M. Lobo, Razvan Peter Figuli, Puja Sethia
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Publication number: 20230305818Abstract: A system for variable replacement in a template artificial intelligence (AI) accelerator code. The system includes: at least one memory; at least one processor communicatively coupled to the at least one memory, and configured for computing at least one table of variables from a template AI accelerator code; and an AI accelerator including a plurality of engines, and communicatively coupled to the at least one processor and the at least one memory. The AI accelerator is configured to create a variable replaced AI accelerator code for the plurality of engines of the AI accelerator from the template AI accelerator code by replacing variables in the template AI accelerator code with actual values from the at least one table of variables.Type: ApplicationFiled: March 24, 2022Publication date: September 28, 2023Inventors: Cedric Lichtenau, Preetham M. Lobo, Razvan Peter Figuli, Puja Sethia
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Patent number: 11693728Abstract: Techniques facilitating voltage droop reduction and/or mitigation in a processor core are provided. In one example, a system can comprise a memory that stores, and a processor that executes, computer executable components. The computer executable components can comprise an observation component that detects one or more events at a first stage of a processor pipeline. An event of the one or more events can be a defined event determined to increase a level of power consumed during a second stage of the processor pipeline. The computer executable components can also comprise an instruction component that applies a voltage droop mitigation countermeasure prior to the increase of the level of power consumed during the second stage of the processor pipeline and a feedback component that provides a notification to the instruction component that indicates a success or a failure of a result of the voltage droop mitigation countermeasure.Type: GrantFiled: February 11, 2022Date of Patent: July 4, 2023Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Giora Biran, Pradip Bose, Alper Buyuktosunoglu, Pierce I-Jen Chuang, Preetham M. Lobo, Ramon Bertran Monfort, Phillip John Restle, Christos Vezyrtzis, Tobias Webel
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Patent number: 11604757Abstract: Processing data in memory using a field programmable gate array by reading a first portion of a data set to a burst block having a first data format, transforming a sub-portion of the first portion, to an element block having a second data format, processing the sub-portion yielding a first results set, transforming the first results set to the first data format of the burst block, and writing the first results set to the burst block.Type: GrantFiled: July 17, 2019Date of Patent: March 14, 2023Assignee: International Business Machines CorporationInventors: Preetham M. Lobo, Gaurav Sulagodu Venkatagiri, Siva Sundar A, Vinod Bussa
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Patent number: 11586267Abstract: Embodiments of the present disclosure relate to managing power provided to a semiconductor circuit to prevent undervoltage conditions. A measured voltage value describing a measured supply voltage at a first subcircuit of a semiconductor circuit can be received, the measured voltage value having a first resolution. A selected metric indicative of a supply voltage present at the first subcircuit can be received, the selected metric having a second resolution higher than the first resolution. The selected metric is calibrated to obtain a calibrated metric when a transition of the measured voltage value occurs.Type: GrantFiled: December 19, 2018Date of Patent: February 21, 2023Assignee: International Business Machines CorporationInventors: Thomas Strach, Preetham M. Lobo, Tobias Webel
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Patent number: 11586265Abstract: Embodiments relate to a system, program product, and method for proactively initiating throttle action on one or more cores in a multicore processing device to mitigate voltage droop therein. The method includes determining, in real-time, an indication of stall events within the core and determining one or more resolutions of the stall events. The method also includes determining, in real-time, a timing margin value for the core and predicting inducement of a voltage droop on the core. The method further includes integrating the resolutions of the stall events and the timing margin value for the core, determining, subject to the predicting, a throttle action for the core, and executing the throttle action on the core.Type: GrantFiled: June 16, 2021Date of Patent: February 21, 2023Assignee: International Business Machines CorporationInventors: Pradeep Bhadravati Parashurama, Alper Buyuktosunoglu, Ramon Bertran Monfort, Tobias Webel, Martin Recktenwald, Preetham M. Lobo, Srinivas Bangalore Purushotham
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Publication number: 20220404890Abstract: Embodiments relate to a system, program product, and method for mitigating voltage overshoot in one or more cores in a multicore processing device including a plurality of cores. The method includes determining, in real-time, an indication of power consumption within each core of the one or more cores. The method also includes determining, through the indication of power consumption, a voltage overshoot condition in the one or more cores. The method further includes increasing, for the one or more cores, a power demand thereof. The method also includes increasing, subject to the increasing the power demand, power delivery to the one or more cores, thereby at least arresting the rate of increase of the voltage overshoot.Type: ApplicationFiled: June 22, 2021Publication date: December 22, 2022Inventors: Pradeep Bhadravati Parashurama, Alper Buyuktosunoglu, Ramon Bertran Monfort, Tobias Webel, Srinivas Bangalore Purushotham, Preetham M. Lobo
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Publication number: 20220404886Abstract: Embodiments relate to a system, program product, and method for proactively initiating throttle action on one or more cores in a multicore processing device to mitigate voltage droop therein. The method includes determining, in real-time, an indication of stall events within the core and determining one or more resolutions of the stall events. The method also includes determining, in real-time, a timing margin value for the core and predicting inducement of a voltage droop on the core. The method further includes integrating the resolutions of the stall events and the timing margin value for the core, determining, subject to the predicting, a throttle action for the core, and executing the throttle action on the core.Type: ApplicationFiled: June 16, 2021Publication date: December 22, 2022Inventors: Pradeep Bhadravati Parashurama, Alper Buyuktosunoglu, Ramon Bertran Monfort, Tobias Webel, Martin Recktenwald, Preetham M. Lobo, Srinivas Bangalore Purushotham
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Publication number: 20220164250Abstract: Techniques facilitating voltage droop reduction and/or mitigation in a processor core are provided. In one example, a system can comprise a memory that stores, and a processor that executes, computer executable components. The computer executable components can comprise an observation component that detects one or more events at a first stage of a processor pipeline. An event of the one or more events can be a defined event determined to increase a level of power consumed during a second stage of the processor pipeline. The computer executable components can also comprise an instruction component that applies a voltage droop mitigation countermeasure prior to the increase of the level of power consumed during the second stage of the processor pipeline and a feedback component that provides a notification to the instruction component that indicates a success or a failure of a result of the voltage droop mitigation countermeasure.Type: ApplicationFiled: February 11, 2022Publication date: May 26, 2022Inventors: Giora Biran, Pradip Bose, Alper Buyuktosunoglu, Pierce I-Jen Chuang, Preetham M. Lobo, Ramon Bertran Monfort, Phillip John Restle, Christos Vezyrtzis, Tobias Webel
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Patent number: 11275644Abstract: Techniques facilitating voltage droop reduction and/or mitigation in a processor core are provided. In one example, a system can comprise a memory that stores, and a processor that executes, computer executable components. The computer executable components can comprise an observation component that detects one or more events at a first stage of a processor pipeline. An event of the one or more events can be a defined event determined to increase a level of power consumed during a second stage of the processor pipeline. The computer executable components can also comprise an instruction component that applies a voltage droop mitigation countermeasure prior to the increase of the level of power consumed during the second stage of the processor pipeline and a feedback component that provides a notification to the instruction component that indicates a success or a failure of a result of the voltage droop mitigation countermeasure.Type: GrantFiled: December 6, 2019Date of Patent: March 15, 2022Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Giora Biran, Pradip Bose, Alper Buyuktosunoglu, Pierce I-Jen Chuang, Preetham M. Lobo, Ramon Bertran Monfort, Phillip John Restle, Christos Vezyrtzis, Tobias Webel
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Patent number: 11188503Abstract: Compression of data is facilitated by locating matches within the data to be compressed. A first technique is used to determine whether there is at least one matching string in the data to be compressed, and a second technique, different from the first technique, is used to determine whether there is at least one matching record in the data to be compressed. Based on there being at least one matching string in the data to be compressed, at least one indication of the at least one matching string is provided to an encoder to facilitate compression of the data. Further, based on there being at least one matching record in the data to be compressed, at least one indication of the at least one matching record is provided to the encoder to facilitate compression of the data. It is transparent to the encoder whether the first technique or the second technique is used to provide one or more matches.Type: GrantFiled: February 18, 2020Date of Patent: November 30, 2021Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Matthias Klein, Damir Anthony Jamsek, Bulent Abali, Ashutosh Misra, Preetham M. Lobo
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Patent number: 11150716Abstract: Various embodiments are provided for providing optimized margins of processors in a computing environment. Margins of voltage, frequency, or a combination thereof may be dynamically monitored and adjusted for a executing a processor based a workload scheduled during an event.Type: GrantFiled: February 5, 2020Date of Patent: October 19, 2021Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Preetham M. Lobo, Pradeep Bhadravati Parashurama, Tobias Webel, Ramon Betran Monfort, Alper Buyuktosunoglu
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Patent number: 11112846Abstract: Embodiments of the present disclosure relate to detecting undervoltage conditions at a subcircuit. A power supply current of a first subcircuit is determined over a first number of previous clock cycles. A cross current flowing between the first subcircuit and a second subcircuit is determined over the first number of previous clock cycles. An estimated momentary supply voltage present at the first subcircuit is then determined based on the power supply current of the first subcircuit over the first number of previous clock cycles and the cross current flowing between the first subcircuit and the second subcircuit over the first number of previous clock cycles.Type: GrantFiled: December 19, 2018Date of Patent: September 7, 2021Assignee: International Business Machines CorporationInventors: Thomas Strach, Preetham M. Lobo, Tobias Webel
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Publication number: 20210255999Abstract: Compression of data is facilitated by locating matches within the data to be compressed. A first technique is used to determine whether there is at least one matching string in the data to be compressed, and a second technique, different from the first technique, is used to determine whether there is at least one matching record in the data to be compressed. Based on there being at least one matching string in the data to be compressed, at least one indication of the at least one matching string is provided to an encoder to facilitate compression of the data. Further, based on there being at least one matching record in the data to be compressed, at least one indication of the at least one matching record is provided to the encoder to facilitate compression of the data. It is transparent to the encoder whether the first technique or the second technique is used to provide one or more matches.Type: ApplicationFiled: February 18, 2020Publication date: August 19, 2021Inventors: Matthias Klein, Damir Anthony Jamsek, Bulent Abali, Ashutosh Misra, Preetham M. Lobo
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Publication number: 20210240247Abstract: Various embodiments are provided for providing optimized margins of processors in a computing environment. Margins of voltage, frequency, or a combination thereof may be dynamically monitored and adjusted for a executing a processor based a workload scheduled during an event.Type: ApplicationFiled: February 5, 2020Publication date: August 5, 2021Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Preetham M. LOBO, Pradeep Bhadravati PARASHURAMA, Tobias WEBEL, Ramon BETRAN MONFORT, Alper BUYUKTOSUNOGLU
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Patent number: 11029742Abstract: Embodiments are disclosed for managing voltage droop. The techniques include performing a first determination that a timing margin is less than a first threshold. The techniques also include performing a second determination that an increase in processor activity exceeds a second threshold. Additionally, the techniques include determining that a voltage droop is indicated based on the first determination and the second determination. Further, the techniques include signaling a plurality of throttling circuits for a corresponding plurality of cores of a computer processor to actuate.Type: GrantFiled: April 1, 2019Date of Patent: June 8, 2021Assignee: International Business Machines CorporationInventors: Tobias Webel, Preetham M Lobo, Alper Buyuktosunoglu, Ramon Bertran Monfort, Pradeep Bhadravati Parashurama, Archit Kapoor
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Patent number: 10955906Abstract: An aspect includes a plurality of throttle controllers having a modular hierarchy comprising a plurality of levels within each of a plurality of processor cores that control a plurality of throttling actions. The throttling actions include dynamic adjustment of execution suspension within the processor cores. A plurality of input throttle events at each of the processor cores is resolved based on the modular hierarchy. A chip controller coupled to the processor cores can synchronize the throttling actions between the processor cores.Type: GrantFiled: February 7, 2019Date of Patent: March 23, 2021Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Preetham M. Lobo, Tobias Webel, Pradeep Bhadravati Parashurama, Alper Buyuktosunoglu
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Patent number: 10955900Abstract: Examples of techniques for speculation throttling for reliability management are described herein. An aspect includes determining that a power state of a processor is above a speculation throttling threshold. Another aspect includes, based on determining that the power state of the processor is above the speculation throttling threshold, throttling speculation in the processor. Another aspect includes determining that the power state of the processor is above a power proxy threshold, wherein the power proxy threshold is higher than the speculation throttling threshold. Another aspect includes, based on determining that the power state of the processor is above the power proxy threshold, enabling a performance throttle unit of the processor.Type: GrantFiled: December 4, 2018Date of Patent: March 23, 2021Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Rahul Rao, Preetham M. Lobo
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Publication number: 20210019280Abstract: Processing data in memory using a field programmable gate array by reading a first portion of a data set to a burst block having a first data format, transforming a sub-portion of the first portion, to an element block having a second data format, processing the sub-portion yielding a first results set, transforming the first results set to the first data format of the burst block, and writing the first results set to the burst block.Type: ApplicationFiled: July 17, 2019Publication date: January 21, 2021Inventors: Preetham M. Lobo, Gaurav Sulagodu Venkatagiri, Siva Sundar A, Vinod Bussa