Patents by Inventor Preetham M Lobo

Preetham M Lobo has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11275644
    Abstract: Techniques facilitating voltage droop reduction and/or mitigation in a processor core are provided. In one example, a system can comprise a memory that stores, and a processor that executes, computer executable components. The computer executable components can comprise an observation component that detects one or more events at a first stage of a processor pipeline. An event of the one or more events can be a defined event determined to increase a level of power consumed during a second stage of the processor pipeline. The computer executable components can also comprise an instruction component that applies a voltage droop mitigation countermeasure prior to the increase of the level of power consumed during the second stage of the processor pipeline and a feedback component that provides a notification to the instruction component that indicates a success or a failure of a result of the voltage droop mitigation countermeasure.
    Type: Grant
    Filed: December 6, 2019
    Date of Patent: March 15, 2022
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Giora Biran, Pradip Bose, Alper Buyuktosunoglu, Pierce I-Jen Chuang, Preetham M. Lobo, Ramon Bertran Monfort, Phillip John Restle, Christos Vezyrtzis, Tobias Webel
  • Patent number: 11188503
    Abstract: Compression of data is facilitated by locating matches within the data to be compressed. A first technique is used to determine whether there is at least one matching string in the data to be compressed, and a second technique, different from the first technique, is used to determine whether there is at least one matching record in the data to be compressed. Based on there being at least one matching string in the data to be compressed, at least one indication of the at least one matching string is provided to an encoder to facilitate compression of the data. Further, based on there being at least one matching record in the data to be compressed, at least one indication of the at least one matching record is provided to the encoder to facilitate compression of the data. It is transparent to the encoder whether the first technique or the second technique is used to provide one or more matches.
    Type: Grant
    Filed: February 18, 2020
    Date of Patent: November 30, 2021
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Matthias Klein, Damir Anthony Jamsek, Bulent Abali, Ashutosh Misra, Preetham M. Lobo
  • Patent number: 11150716
    Abstract: Various embodiments are provided for providing optimized margins of processors in a computing environment. Margins of voltage, frequency, or a combination thereof may be dynamically monitored and adjusted for a executing a processor based a workload scheduled during an event.
    Type: Grant
    Filed: February 5, 2020
    Date of Patent: October 19, 2021
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Preetham M. Lobo, Pradeep Bhadravati Parashurama, Tobias Webel, Ramon Betran Monfort, Alper Buyuktosunoglu
  • Patent number: 11112846
    Abstract: Embodiments of the present disclosure relate to detecting undervoltage conditions at a subcircuit. A power supply current of a first subcircuit is determined over a first number of previous clock cycles. A cross current flowing between the first subcircuit and a second subcircuit is determined over the first number of previous clock cycles. An estimated momentary supply voltage present at the first subcircuit is then determined based on the power supply current of the first subcircuit over the first number of previous clock cycles and the cross current flowing between the first subcircuit and the second subcircuit over the first number of previous clock cycles.
    Type: Grant
    Filed: December 19, 2018
    Date of Patent: September 7, 2021
    Assignee: International Business Machines Corporation
    Inventors: Thomas Strach, Preetham M. Lobo, Tobias Webel
  • Publication number: 20210255999
    Abstract: Compression of data is facilitated by locating matches within the data to be compressed. A first technique is used to determine whether there is at least one matching string in the data to be compressed, and a second technique, different from the first technique, is used to determine whether there is at least one matching record in the data to be compressed. Based on there being at least one matching string in the data to be compressed, at least one indication of the at least one matching string is provided to an encoder to facilitate compression of the data. Further, based on there being at least one matching record in the data to be compressed, at least one indication of the at least one matching record is provided to the encoder to facilitate compression of the data. It is transparent to the encoder whether the first technique or the second technique is used to provide one or more matches.
    Type: Application
    Filed: February 18, 2020
    Publication date: August 19, 2021
    Inventors: Matthias Klein, Damir Anthony Jamsek, Bulent Abali, Ashutosh Misra, Preetham M. Lobo
  • Publication number: 20210240247
    Abstract: Various embodiments are provided for providing optimized margins of processors in a computing environment. Margins of voltage, frequency, or a combination thereof may be dynamically monitored and adjusted for a executing a processor based a workload scheduled during an event.
    Type: Application
    Filed: February 5, 2020
    Publication date: August 5, 2021
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Preetham M. LOBO, Pradeep Bhadravati PARASHURAMA, Tobias WEBEL, Ramon BETRAN MONFORT, Alper BUYUKTOSUNOGLU
  • Patent number: 11029742
    Abstract: Embodiments are disclosed for managing voltage droop. The techniques include performing a first determination that a timing margin is less than a first threshold. The techniques also include performing a second determination that an increase in processor activity exceeds a second threshold. Additionally, the techniques include determining that a voltage droop is indicated based on the first determination and the second determination. Further, the techniques include signaling a plurality of throttling circuits for a corresponding plurality of cores of a computer processor to actuate.
    Type: Grant
    Filed: April 1, 2019
    Date of Patent: June 8, 2021
    Assignee: International Business Machines Corporation
    Inventors: Tobias Webel, Preetham M Lobo, Alper Buyuktosunoglu, Ramon Bertran Monfort, Pradeep Bhadravati Parashurama, Archit Kapoor
  • Patent number: 10955906
    Abstract: An aspect includes a plurality of throttle controllers having a modular hierarchy comprising a plurality of levels within each of a plurality of processor cores that control a plurality of throttling actions. The throttling actions include dynamic adjustment of execution suspension within the processor cores. A plurality of input throttle events at each of the processor cores is resolved based on the modular hierarchy. A chip controller coupled to the processor cores can synchronize the throttling actions between the processor cores.
    Type: Grant
    Filed: February 7, 2019
    Date of Patent: March 23, 2021
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Preetham M. Lobo, Tobias Webel, Pradeep Bhadravati Parashurama, Alper Buyuktosunoglu
  • Patent number: 10955900
    Abstract: Examples of techniques for speculation throttling for reliability management are described herein. An aspect includes determining that a power state of a processor is above a speculation throttling threshold. Another aspect includes, based on determining that the power state of the processor is above the speculation throttling threshold, throttling speculation in the processor. Another aspect includes determining that the power state of the processor is above a power proxy threshold, wherein the power proxy threshold is higher than the speculation throttling threshold. Another aspect includes, based on determining that the power state of the processor is above the power proxy threshold, enabling a performance throttle unit of the processor.
    Type: Grant
    Filed: December 4, 2018
    Date of Patent: March 23, 2021
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Rahul Rao, Preetham M. Lobo
  • Publication number: 20210019280
    Abstract: Processing data in memory using a field programmable gate array by reading a first portion of a data set to a burst block having a first data format, transforming a sub-portion of the first portion, to an element block having a second data format, processing the sub-portion yielding a first results set, transforming the first results set to the first data format of the burst block, and writing the first results set to the burst block.
    Type: Application
    Filed: July 17, 2019
    Publication date: January 21, 2021
    Inventors: Preetham M. Lobo, Gaurav Sulagodu Venkatagiri, Siva Sundar A, Vinod Bussa
  • Publication number: 20200310516
    Abstract: Embodiments are disclosed for managing voltage droop. The techniques include performing a first determination that a timing margin is less than a first threshold. The techniques also include performing a second determination that an increase in processor activity exceeds a second threshold. Additionally, the techniques include determining that a voltage droop is indicated based on the first determination and the second determination. Further, the techniques include signaling a plurality of throttling circuits for a corresponding plurality of cores of a computer processor to actuate.
    Type: Application
    Filed: April 1, 2019
    Publication date: October 1, 2020
    Inventors: Tobias Webel, Preetham M. Lobo, Alper Buyuktosunoglu, Ramon Bertran Monfort, Pradeep Bhadravati Parashurama, Archit Kapoor
  • Publication number: 20200257349
    Abstract: An aspect includes a plurality of throttle controllers having a modular hierarchy comprising a plurality of levels within each of a plurality of processor cores that control a plurality of throttling actions. The throttling actions include dynamic adjustment of execution suspension within the processor cores. A plurality of input throttle events at each of the processor cores is resolved based on the modular hierarchy. A chip controller coupled to the processor cores can synchronize the throttling actions between the processor cores.
    Type: Application
    Filed: February 7, 2019
    Publication date: August 13, 2020
    Inventors: Preetham M. Lobo, Tobias Webel, Pradeep Bhadravati Parashurama, Alper Buyuktosunoglu
  • Patent number: 10725517
    Abstract: A semiconductor circuit including a first subcircuit, at least a second subcircuit, and power management circuitry. The power management circuitry is operable for estimating a metric indicative of a momentary supply voltage present at the first subcircuit based on a power supply current of the first subcircuit and a cross current flowing between the first subcircuit and the second subcircuit.
    Type: Grant
    Filed: October 8, 2019
    Date of Patent: July 28, 2020
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Preetham M. Lobo, Thomas Strach, Tobias Webel
  • Publication number: 20200201413
    Abstract: Embodiments of the present disclosure relate to managing power provided to a semiconductor circuit to prevent undervoltage conditions. A measured voltage value describing a measured supply voltage at a first subcircuit of a semiconductor circuit can be received, the measured voltage value having a first resolution. A selected metric indicative of a supply voltage present at the first subcircuit can be received, the selected metric having a second resolution higher than the first resolution. The selected metric is calibrated to obtain a calibrated metric when a transition of the measured voltage value occurs.
    Type: Application
    Filed: December 19, 2018
    Publication date: June 25, 2020
    Inventors: Thomas Strach, Preetham M. Lobo, Tobias Webel
  • Publication number: 20200201407
    Abstract: Embodiments of the present disclosure relate to detecting undervoltage conditions at a subcircuit. A power supply current of a first subcircuit is determined over a first number of previous clock cycles. A cross current flowing between the first subcircuit and a second subcircuit is determined over the first number of previous clock cycles. An estimated momentary supply voltage present at the first subcircuit is then determined based on the power supply current of the first subcircuit over the first number of previous clock cycles and the cross current flowing between the first subcircuit and the second subcircuit over the first number of previous clock cycles.
    Type: Application
    Filed: December 19, 2018
    Publication date: June 25, 2020
    Inventors: Thomas Strach, Preetham M. Lobo, Tobias Webel
  • Publication number: 20200174542
    Abstract: Examples of techniques for speculation throttling for reliability management are described herein. An aspect includes determining that a power state of a processor is above a speculation throttling threshold. Another aspect includes, based on determining that the power state of the processor is above the speculation throttling threshold, throttling speculation in the processor. Another aspect includes determining that the power state of the processor is above a power proxy threshold, wherein the power proxy threshold is higher than the speculation throttling threshold. Another aspect includes, based on determining that the power state of the processor is above the power proxy threshold, enabling a performance throttle unit of the processor.
    Type: Application
    Filed: December 4, 2018
    Publication date: June 4, 2020
    Inventors: Rahul Rao, Preetham M. Lobo
  • Publication number: 20200110656
    Abstract: Techniques facilitating voltage droop reduction and/or mitigation in a processor core are provided. In one example, a system can comprise a memory that stores, and a processor that executes, computer executable components. The computer executable components can comprise an observation component that detects one or more events at a first stage of a processor pipeline. An event of the one or more events can be a defined event determined to increase a level of power consumed during a second stage of the processor pipeline. The computer executable components can also comprise an instruction component that applies a voltage droop mitigation countermeasure prior to the increase of the level of power consumed during the second stage of the processor pipeline and a feedback component that provides a notification to the instruction component that indicates a success or a failure of a result of the voltage droop mitigation countermeasure.
    Type: Application
    Filed: December 6, 2019
    Publication date: April 9, 2020
    Inventors: Giora Biran, Pradip Bose, Alper Buyuktosunoglu, Pierce I-Jen Chuang, Preetham M. Lobo, Ramon Bertran Monfort, Phillip John Restle, Christos Vezyrtzis, Tobias Webel
  • Patent number: 10598526
    Abstract: Embodiments include methods, and computer system, and computer program products for performing test and calibration of integrated sensors on a processor chip. Aspects include: initializing, by a tester program, an on-chip service engine of processor chip, performing and completing, by on-chip service engine, test and calibration of integrated sensors. The method may also include: loading and decoding tester program into an on-chip service engine memory, testing and calibrating each integrated sensor, which may include: selecting an integrated sensor for test and calibration, loading sensor test and calibration patterns and parameters, and sensor test code, and executing the sensor test code to test and calibrate integrated sensors, writing results of the test and calibration to a predetermined location of the on-chip service engine memory, and writing a return code of test and calibration to another predetermined location of on-chip service engine memory, when every integrated sensor is tested and calibrated.
    Type: Grant
    Filed: March 8, 2016
    Date of Patent: March 24, 2020
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Mitesh Agrawal, Preetham M. Lobo, Franco Motika, John D. Parker, Gerard M. Salem, Tobias Webel
  • Patent number: 10571519
    Abstract: Embodiments include methods, and computer system, and computer program products for performing system functional test on a chip having partial-good portions. Aspects include: initializing, by system functional test software, a service engine of the chip, performing, by service engine, system functional test, and completing system functional test of chip. The chip may include service engine, a service engine memory and one or more “partial-good” portions. The initializing may include: loading system functional test software into the service engine memory, identifying each “partial-good” portion of the chip, writing a “partial-good” parameter for each “partial-good” portion of the chip identified to service engine memory, and triggering execution of system functional test. Method may include: decoding system functional test software, retrieving “partial-good” parameters, initializing “partial-good” portions of chip, and performing system functional test on “partial-good” portions of chip.
    Type: Grant
    Filed: March 8, 2016
    Date of Patent: February 25, 2020
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Mitesh A. Agrawal, Preetham M. Lobo, Franco Motika, John D. Parker, Gerard M. Salem
  • Patent number: 10552250
    Abstract: Techniques facilitating voltage droop reduction and/or mitigation in a processor core are provided. In one example, a system can comprise a memory that stores, and a processor that executes, computer executable components. The computer executable components can comprise an observation component that detects one or more events at a first stage of a processor pipeline. An event of the one or more events can be a defined event determined to increase a level of power consumed during a second stage of the processor pipeline. The computer executable components can also comprise an instruction component that applies a voltage droop mitigation countermeasure prior to the increase of the level of power consumed during the second stage of the processor pipeline and a feedback component that provides a notification to the instruction component that indicates a success or a failure of a result of the voltage droop mitigation countermeasure.
    Type: Grant
    Filed: October 10, 2017
    Date of Patent: February 4, 2020
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Giora Biran, Pradip Bose, Alper Buyuktosunoglu, Pierce I-Jen Chuang, Preetham M. Lobo, Ramon Bertran Monfort, Phillip John Restle, Christos Vezyrtzis, Tobias Webel