Patents by Inventor Preetham M Lobo

Preetham M Lobo has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10552250
    Abstract: Techniques facilitating voltage droop reduction and/or mitigation in a processor core are provided. In one example, a system can comprise a memory that stores, and a processor that executes, computer executable components. The computer executable components can comprise an observation component that detects one or more events at a first stage of a processor pipeline. An event of the one or more events can be a defined event determined to increase a level of power consumed during a second stage of the processor pipeline. The computer executable components can also comprise an instruction component that applies a voltage droop mitigation countermeasure prior to the increase of the level of power consumed during the second stage of the processor pipeline and a feedback component that provides a notification to the instruction component that indicates a success or a failure of a result of the voltage droop mitigation countermeasure.
    Type: Grant
    Filed: October 10, 2017
    Date of Patent: February 4, 2020
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Giora Biran, Pradip Bose, Alper Buyuktosunoglu, Pierce I-Jen Chuang, Preetham M. Lobo, Ramon Bertran Monfort, Phillip John Restle, Christos Vezyrtzis, Tobias Webel
  • Publication number: 20200033927
    Abstract: A semiconductor circuit including a first subcircuit, at least a second subcircuit, and power management circuitry. The power management circuitry is operable for estimating a metric indicative of a momentary supply voltage present at the first subcircuit based on a power supply current of the first subcircuit and a cross current flowing between the first subcircuit and the second subcircuit.
    Type: Application
    Filed: October 8, 2019
    Publication date: January 30, 2020
    Inventors: Preetham M. Lobo, Thomas Strach, Tobias Webel
  • Patent number: 10481662
    Abstract: A semiconductor circuit including a first subcircuit, at least a second subcircuit, and power management circuitry. The power management circuitry is operable for estimating a metric indicative of a momentary supply voltage present at the first subcircuit based on a power supply current of the first subcircuit and a cross current flowing between the first subcircuit and the second subcircuit.
    Type: Grant
    Filed: November 21, 2016
    Date of Patent: November 19, 2019
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Preetham M. Lobo, Thomas Strach, Tobias Webel
  • Patent number: 10365132
    Abstract: Embodiments include methods, and computer system, and computer program products for performing test and calibration of integrated sensors on a processor chip. Aspects include: initializing, by a tester program, an on-chip service engine of processor chip, performing and completing, by on-chip service engine, test and calibration of integrated sensors. The method may also include: loading and decoding tester program into an on-chip service engine memory, testing and calibrating each integrated sensor, which may include: selecting an integrated sensor for test and calibration, loading sensor test and calibration patterns and parameters, and sensor test code, and executing the sensor test code to test and calibrate integrated sensors, writing results of the test and calibration to a predetermined location of the on-chip service engine memory, and writing a return code of test and calibration to another predetermined location of on-chip service engine memory, when every integrated sensor is tested and calibrated.
    Type: Grant
    Filed: June 25, 2018
    Date of Patent: July 30, 2019
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Mitesh Agrawal, Preetham M. Lobo, Franco Motika, John D. Parker, Gerard M. Salem, Tobias Webel
  • Publication number: 20190108087
    Abstract: Techniques facilitating voltage droop reduction and/or mitigation in a processor core are provided. In one example, a system can comprise a memory that stores, and a processor that executes, computer executable components. The computer executable components can comprise an observation component that detects one or more events at a first stage of a processor pipeline. An event of the one or more events can be a defined event determined to increase a level of power consumed during a second stage of the processor pipeline. The computer executable components can also comprise an instruction component that applies a voltage droop mitigation countermeasure prior to the increase of the level of power consumed during the second stage of the processor pipeline and a feedback component that provides a notification to the instruction component that indicates a success or a failure of a result of the voltage droop mitigation countermeasure.
    Type: Application
    Filed: October 10, 2017
    Publication date: April 11, 2019
    Inventors: Giora Biran, Pradip Bose, Alper Buyuktosunoglu, Pierce I-Jen Chuang, Preetham M. Lobo, Ramon Bertran Monfort, Phillip John Restle, Christos Vezyrtzis, Tobias Webel
  • Publication number: 20180306610
    Abstract: Embodiments include methods, and computer system, and computer program products for performing test and calibration of integrated sensors on a processor chip. Aspects include: initializing, by a tester program, an on-chip service engine of processor chip, performing and completing, by on-chip service engine, test and calibration of integrated sensors. The method may also include: loading and decoding tester program into an on-chip service engine memory, testing and calibrating each integrated sensor, which may include: selecting an integrated sensor for test and calibration, loading sensor test and calibration patterns and parameters, and sensor test code, and executing the sensor test code to test and calibrate integrated sensors, writing results of the test and calibration to a predetermined location of the on-chip service engine memory, and writing a return code of test and calibration to another predetermined location of on-chip service engine memory, when every integrated sensor is tested and calibrated.
    Type: Application
    Filed: June 25, 2018
    Publication date: October 25, 2018
    Inventors: Mitesh Agrawal, Preetham M. Lobo, Franco Motika, John D. Parker, Gerard M. Salem, Tobias Webel
  • Patent number: 10048734
    Abstract: Adaptive power capping in a chip that includes a plurality of cores in a processing system is provided. An active power demand for the chip is dynamically determined based on observed events of the cores. An average temperature of the chip is computed using one or more on-chip thermal sensors in the cores to estimate leakage power of the chip. A power capping threshold that incorporates the estimate of leakage power is determined based on the average temperature of the chip. Power capping is performed by throttling the cores based on determining that the active power demand for the chip exceeds the power capping threshold.
    Type: Grant
    Filed: December 5, 2017
    Date of Patent: August 14, 2018
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Charles R. Lefurgy, Preetham M. Lobo, Richard F. Rizzolo, Malcolm S. Allen-Ware, Tobias Webel
  • Publication number: 20180088650
    Abstract: A semiconductor circuit including a first subcircuit, at least a second subcircuit, and power management circuitry. The power management circuitry is operable for estimating a metric indicative of a momentary supply voltage present at the first subcircuit based on a power supply current of the first subcircuit and a cross current flowing between the first subcircuit and the second subcircuit.
    Type: Application
    Filed: November 21, 2016
    Publication date: March 29, 2018
    Inventors: Preetham M. Lobo, Thomas Strach, Tobias Webel
  • Publication number: 20180081413
    Abstract: Adaptive power capping in a chip that includes a plurality of cores in a processing system is provided. An active power demand for the chip is dynamically determined based on observed events of the cores. An average temperature of the chip is computed using one or more on-chip thermal sensors in the cores to estimate leakage power of the chip. A power capping threshold that incorporates the estimate of leakage power is determined based on the average temperature of the chip. Power capping is performed by throttling the cores based on determining that the active power demand for the chip exceeds the power capping threshold.
    Type: Application
    Filed: December 5, 2017
    Publication date: March 22, 2018
    Inventors: Charles R. Lefurgy, Preetham M. Lobo, Richard F. Rizzolo, Malcolm S. Allen-Ware, Tobias Webel
  • Patent number: 9874917
    Abstract: Adaptive power capping in a chip that includes a plurality of cores in a processing system is provided. An active power demand for the chip is dynamically determined based on observed events of the cores. An average temperature of the chip is computed using one or more on-chip thermal sensors in the cores to estimate leakage power of the chip. A power capping threshold that incorporates the estimate of leakage power is determined based on the average temperature of the chip. Power capping is performed by throttling the cores based on determining that the active power demand for the chip exceeds the power capping threshold.
    Type: Grant
    Filed: January 4, 2016
    Date of Patent: January 23, 2018
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Charles R. Lefurgy, Preetham M. Lobo, Richard F. Rizzolo, Malcolm S. Allen-Ware, Tobias Webel
  • Publication number: 20170261551
    Abstract: Embodiments include methods, and computer system, and computer program products for performing system functional test on a chip having partial-good portions. Aspects include: initializing, by system functional test software, a service engine of the chip, performing, by service engine, system functional test, and completing system functional test of chip. The chip may include service engine, a service engine memory and one or more “partial-good” portions. The initializing may include: loading system functional test software into the service engine memory, identifying each “partial-good” portion of the chip, writing a “partial-good” parameter for each “partial-good” portion of the chip identified to service engine memory, and triggering execution of system functional test. Method may include: decoding system functional test software, retrieving “partial-good” parameters, initializing “partial-good” portions of chip, and performing system functional test on “partial-good” portions of chip.
    Type: Application
    Filed: March 8, 2016
    Publication date: September 14, 2017
    Inventors: Mitesh A. Agrawal, Preetham M. Lobo, Franco Motika, John D. Parker, Gerard M. Salem
  • Publication number: 20170261354
    Abstract: Embodiments include methods, and computer system, and computer program products for performing test and calibration of integrated sensors on a processor chip. Aspects include: initializing, by a tester program, an on-chip service engine of processor chip, performing and completing, by on-chip service engine, test and calibration of integrated sensors. The method may also include: loading and decoding tester program into an on-chip service engine memory, testing and calibrating each integrated sensor, which may include: selecting an integrated sensor for test and calibration, loading sensor test and calibration patterns and parameters, and sensor test code, and executing the sensor test code to test and calibrate integrated sensors, writing results of the test and calibration to a predetermined location of the on-chip service engine memory, and writing a return code of test and calibration to another predetermined location of on-chip service engine memory, when every integrated sensor is tested and calibrated.
    Type: Application
    Filed: March 8, 2016
    Publication date: September 14, 2017
    Inventors: Mitesh Agrawal, Preetham M. Lobo, Franco Motika, John D. Parker, Gerald M. Salem, Tobias Webel
  • Publication number: 20170192477
    Abstract: Adaptive power capping in a chip that includes a plurality of cores in a processing system is provided. An active power demand for the chip is dynamically determined based on observed events of the cores. An average temperature of the chip is computed using one or more on-chip thermal sensors in the cores to estimate leakage power of the chip. A power capping threshold that incorporates the estimate of leakage power is determined based on the average temperature of the chip. Power capping is performed by throttling the cores based on determining that the active power demand for the chip exceeds the power capping threshold.
    Type: Application
    Filed: January 4, 2016
    Publication date: July 6, 2017
    Inventors: Charles R. Lefurgy, Preetham M. Lobo, Richard F. Rizzolo, Malcolm S. Allen-Ware, Tobias Webel
  • Patent number: 9575529
    Abstract: A processor is provided having a common supply rail, and one or more processor cores, where the one or more processor cores share the common supply rail. Each processor core(s) includes a core dIPC value output and a core throttling signal input, and a chip power management logic, which has at least one input for inputting the core dIPC value, a threshold register for a dIPC threshold value, a chip dIPC register for a current global dIPC value, at least one chip dIPC history register for a historic global dIPC value, a subtractor providing an absolute difference of an average historic global dIPC derived from the historic global dIPC value and the current global dIPC value, a magnitude comparator providing a throttling signal when the absolute difference is above the dIPC threshold value, and at least one output for outputting a core throttling signal to the processor core(s).
    Type: Grant
    Filed: September 24, 2015
    Date of Patent: February 21, 2017
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Brian W. Curran, Preetham M. Lobo, Richard F. Rizzolo, James D. Warnock, Tobias Webel
  • Patent number: 9378048
    Abstract: Embodiments include receiving, at a microcontroller of a chip, a request to execute a first task having a first priority. Embodiments further include determining that a second task having a second priority is currently executing. Embodiments further include determining that the first priority is higher than the second priority. Embodiments further include determining whether a value in a register indicates that the second task can be interrupted. If it is determined that the second task can be interrupted, embodiments further include triggering execution of the second task. If it is determined that the second task cannot be interrupted, embodiments further include waiting for lapse of a time period since receipt of the request to execute the first task, and interrupting the second task upon detecting lapse of the time period, or detecting, prior to the lapse of the time period, that the second task can be interrupted.
    Type: Grant
    Filed: June 11, 2014
    Date of Patent: June 28, 2016
    Assignee: International Business Machines Corporation
    Inventors: Bishop Brock, Tilman Gloekler, Andreas Koenig, Cedric Lichtenau, Preetham M. Lobo
  • Patent number: 9372717
    Abstract: Embodiments include an apparatus comprising a processor and a computer readable storage medium having computer usable program code. The computer usable program code can be configured to determine whether priority of a requested task is higher than a priority of a currently executing task. The computer usable program code can be further configured to determine whether a value indicates that the currently executing task can be interrupted. The computer usable program code can be configured to trigger execution of the requested task on the processor, if the value indicates that the currently executed task can be interrupted. The computer usable program code can be further configured to wait for lapse of a time period and, interrupt the currently executing task upon detection of lapse of the time period or detection of a change to the value, if the value indicates that the currently executing task cannot be interrupted.
    Type: Grant
    Filed: May 8, 2014
    Date of Patent: June 21, 2016
    Assignee: International Business Machines Corporation
    Inventors: Bishop Brock, Tilman Gloekler, Andreas Koenig, Cedric Lichtenau, Preetham M Lobo
  • Publication number: 20160098070
    Abstract: A processor is provided having a common supply rail, and one or more processor cores, where the one or more processor cores share the common supply rail. Each processor core(s) includes a core dIPC value output and a core throttling signal input, and a chip power management logic, which has at least one input for inputting the core dIPC value, a threshold register for a dIPC threshold value, a chip dIPC register for a current global dIPC value, at least one chip dIPC history register for a historic global dIPC value, a subtractor providing an absolute difference of an average historic global dIPC derived from the historic global dIPC value and the current global dIPC value, a magnitude comparator providing a throttling signal when the absolute difference is above the dIPC threshold value, and at least one output for outputting a core throttling signal to the processor core(s).
    Type: Application
    Filed: September 24, 2015
    Publication date: April 7, 2016
    Inventors: Brian W. CURRAN, Preetham M. LOBO, Richard F. RIZZOLO, James D. WARNOCK, Tobias WEBEL
  • Publication number: 20140344823
    Abstract: Embodiments include an apparatus comprising a processor and a computer readable storage medium having computer usable program code. The computer usable program code can be configured to determine whether priority of a requested task is higher than a priority of a currently executing task. The computer usable program code can be further configured to determine whether a value indicates that the currently executing task can be interrupted. The computer usable program code can be configured to trigger execution of the requested task on the processor, if the value indicates that the currently executed task can be interrupted. The computer usable program code can be further configured to wait for lapse of a time period and, interrupt the currently executing task upon detection of lapse of the time period or detection of a change to the value, if the value indicates that the currently executing task cannot be interrupted.
    Type: Application
    Filed: May 8, 2014
    Publication date: November 20, 2014
    Applicant: International Business Machines Corporation
    Inventors: Bishop Brock, Tilman Gloekler, Andreas Koenig, Cedric Lichtenau, Preetham M Lobo
  • Publication number: 20140344824
    Abstract: Embodiments include receiving, at a microcontroller of a chip, a request to execute a first task having a first priority. Embodiments further include determining that a second task having a second priority is currently executing. Embodiments further include determining that the first priority is higher than the second priority. Embodiments further include determining whether a value in a register indicates that the second task can be interrupted. If it is determined that the second task can be interrupted, embodiments further include triggering execution of the second task. If it is determined that the second task cannot be interrupted, embodiments further include waiting for lapse of a time period since receipt of the request to execute the first task, and interrupting the second task upon detecting lapse of the time period, or detecting, prior to the lapse of the time period, that the second task can be interrupted.
    Type: Application
    Filed: June 11, 2014
    Publication date: November 20, 2014
    Inventors: Bishop Brock, Tilman Gloekler, Andreas Koenig, Cedric Lichtenau, Preetham M. Lobo