Abstract: A switching converter controller includes: a stopband controller having a stopband controller input and a stopband controller output, the stopband controller is configured to provide stopband information at the stopband controller output responsive to a reference signal; a pulse-frequency modulation (PFM) controller having a first PFM controller input, a second PFM controller input and a PFM controller output, the first PFM controller input configured to receive a feedback error signal, the second PFM controller input coupled to the stopband controller output, and the PFM controller configured to selectively adjust a clock signal at the PFM controller output based on the feedback error signal and the stopband information; and a driver circuit having a driver circuit input coupled to the PFM controller output and configured to receive the clock signal, and having a driver circuit output adapted to be coupled to a power stage switch.

Abstract: A DC-DC converter circuit includes an error amplifier, a comparator, an oscillator, and a control circuit. The error amplifier is configured to generate an error signal. The control circuit is coupled to the error amplifier, the comparator, and the oscillator. The control circuit is configured to generate an oscillator control signal to control a frequency of the oscillator based on the error signal, and to generate a peak control signal provided to the comparator based on the error signal. The control circuit is also configured to switch, based on the error signal, between a first modulation mode and a second modulation mode during a transition mode, and in the transition mode, generate the oscillator control signal based on the peak control signal and the error signal.

Abstract: A switching converter controller includes: a stopband controller having a stopband controller input and a stopband controller output, the stopband controller is configured to provide stopband information at the stopband controller output responsive to a reference signal; a pulse-frequency modulation (PFM) controller having a first PFM controller input, a second PFM controller input and a PFM controller output, the first PFM controller input configured to receive a feedback error signal, the second PFM controller input coupled to the stopband controller output, and the PFM controller configured to selectively adjust a clock signal at the PFM controller output based on the feedback error signal and the stopband information; and a driver circuit having a driver circuit input coupled to the PFM controller output and configured to receive the clock signal, and having a driver circuit output adapted to be coupled to a power stage switch.

Abstract: A DC-DC converter includes an output terminal, a reference voltage source, an error amplifier, and a compensation circuit. The error amplifier is coupled to the output terminal and the reference voltage source. The error amplifier is configured to generate an error signal representative of a difference between a voltage at the output terminal and a reference voltage provided by the reference voltage source. The compensation circuit is coupled to the error amplifier. The compensation circuit includes a resistor, a capacitor, and a switch control circuit. The resistor is coupled to the error amplifier. The capacitor is coupled to the resistor. The switch control circuit is configured to modulate connection of the resistor to the capacitor based on a switching frequency of the DC-DC converter.

Abstract: A switching converter controller includes: a stopband controller having a stopband controller input and a stopband controller output, the stopband controller is configured to provide stopband information at the stopband controller output responsive to a reference signal; a pulse-frequency modulation (PFM) controller having a first PFM controller input, a second PFM controller input and a PFM controller output, the first PFM controller input configured to receive a feedback error signal, the second PFM controller input coupled to the stopband controller output, and the PFM controller configured to selectively adjust a clock signal at the PFM controller output based on the feedback error signal and the stopband information; and a driver circuit having a driver circuit input coupled to the PFM controller output and configured to receive the clock signal, and having a driver circuit output adapted to be coupled to a power stage switch.

Abstract: In an example, a system includes a switching voltage converter including a first field effect transistor (FET) and a second FET, the switching voltage converter configured to receive an input voltage and provide an output voltage. The system also includes a voltage to current converter coupled to the switching voltage converter and an oscillator, the voltage to current converter configured to receive an error voltage of the output voltage and provide an oscillator current to the oscillator. The system includes a comparator coupled to the oscillator and configured to compare the oscillator current to a reference current, where an output of the comparator is configured to skip a pulse of an oscillator output responsive to the oscillator current being less than the reference current.

Abstract: A converter operable to convert an input voltage at an input node to an output voltage at an output node coupled to a load by switching on and off a transistor at a switching frequency, the converter comprising: an error amplifier circuit having a first input coupled to a reference voltage, a second input coupled to the output node through a resistive divider, a first output operable to output a control current and a second output operable to output a current equivalent to the control current; a peak current comparator circuit having a first input coupled to the second output of the error amplifier circuit, a second input and an output, the second input is coupled to the input node through an inductor; an off-time timer circuit having an input coupled to the first output of the error amplifier circuit and an output, the off-time timer circuit operable to set the switching frequency based on the control current; and a control circuit having a first input coupled to the output of the peak current comparator cir

Abstract: A DC-DC converter includes an output terminal, a reference voltage source, an error amplifier, and a compensation circuit. The error amplifier is coupled to the output terminal and the reference voltage source. The error amplifier is configured to generate an error signal representative of a difference between a voltage at the output terminal and a reference voltage provided by the reference voltage source. The compensation circuit is coupled to the error amplifier. The compensation circuit includes a resistor, a capacitor, and a switch control circuit. The resistor is coupled to the error amplifier. The capacitor is coupled to the resistor. The switch control circuit is configured to modulate connection of the resistor to the capacitor based on a switching frequency of the DC-DC converter.

Abstract: A converter having an input adapted to be connected to an input voltage and an output adapted to supply an output voltage, the converter comprising: a high-side switch having a first current terminal, a second current terminal and a first control terminal, the first current terminal is coupled to the input voltage and the second current terminal is coupled to a switching node; a high-side driver circuit having an input, a first supply input, a second supply input and an output coupled to the first control terminal, the second supply input is coupled to the switching node; a bootstrap capacitor having a first terminal and a second terminal, the first terminal coupled to the first supply input and the second terminal coupled to the second supply input; a switch having a first terminal and a second terminal, the first terminal of the switch is coupled to the first terminal of the bootstrap capacitor and the second terminal of the switch is connected to a supply voltage (VDD volts above ground).

Abstract: A converter operable to convert an input voltage at an input node to an output voltage at an output node coupled to a load by switching on and off a transistor at a switching frequency, the converter comprising: an error amplifier circuit having a first input coupled to a reference voltage, a second input coupled to the output node through a resistive divider, a first output operable to output a control current and a second output operable to output a current equivalent to the control current; a peak current comparator circuit having a first input coupled to the second output of the error amplifier circuit, a second input and an output, the second input is coupled to the input node through an inductor; an off-time timer circuit having an input coupled to the first output of the error amplifier circuit and an output, the off-time timer circuit operable to set the switching frequency based on the control current; and a control circuit having a first input coupled to the output of the peak current comparator cir

Abstract: The invention generally relates to phase locked loops (PLL), and more specifically to ultra-low bandwidth phase locked loops. The invention may be for example embodied in an integrated circuit implementing a phase locked loop or a method for operating a phase locked loop. The invention provides a PLL with a control stage that uses only two storage cells, a counter and a digital-to-analog (DAC) converter. In comparison to prior-art PLLs using storage cells the configuration of the invention's control stage reduces the chip area required for the PLL reduced. The invention further suggests PVT compensation mechanisms for a PLL and implementing a PLL that has lower peaking in its frequency response, which results in better settling response.

Abstract: The invention generally relates to phase locked loops (PLL), and more specifically to ultra-low bandwidth phase locked loops. The invention may be for example embodied in an integrated circuit implementing a phase locked loop or a method for operating a phase locked loop. The invention provides a PLL with a control stage that uses only two storage cells, a counter and a digital-to-analog (DAC) converter. In comparison to prior-art PLLs using storage cells the configuration of the invention's control stage reduces the chip area required for the PLL reduced. The invention further suggests PVT compensation mechanisms for a PLL and implementing a PLL that has lower peaking in its frequency response, which results in better settling response.

Abstract: A buffer is provided. The buffer includes a buffering stage that receives an enable signal and an input signal and that provides an output signal and a bandgap stage that is coupled to the buffering stage and that is activated and deactivated by the enable signal. In particular, the buffering stage includes a buffering substage that includes a buffering transistor that is coupled to the input stage, wherein the buffering transistor is formed on a substrate, and wherein the buffering transistor has a channel with a doping concentration that is approximately the same as the substrate.

Abstract: A phase locked loop (PLL) is provided. The PLL includes a control stage comprising N storage elements each having an output coupled to the output of the control stage. The N storage elements being coupled in a chain, and each storage element being configurable in an analog mode, where a stored signal at the storage node of the storage element is changed continuously in response to the output signal of a charge pump. Each storage element is configurable in a digital mode in which the stored value is one value out of a predetermined set of values, and the storage element can assume the analog mode if a preceding storage element and a subsequent storage element are in the digital mode and have different values of the stored signal.

Abstract: An electronic device is provided that includes a power-on-reset (POR) circuit. The POR circuit includes a trigger stage configured to change an output if a first power supply voltage level exceeds a threshold voltage level and a first inverter and a second inverter being cross-coupled. An output of the second inverter is the POR output of the power-up reset circuit. The output is coupled to the trigger stage for switching the trigger stage off in response to a change of a signal at the output of the second inverter. The first inverter is dimensioned to follow with a voltage level at an output an initially rising slope of the first power supply voltage level and the second inverter is dimensioned to keep a voltage level at an output at a second power supply voltage level during the initially rising slope of the first power supply voltage level.

Abstract: A buffer is provided. The buffer includes a buffering stage that receives an enable signal and an input signal and that provides an output signal and a bandgap stage that is coupled to the buffering stage and that is activated and deactivated by the enable signal. In particular, the buffering stage includes a buffering substage that includes a buffering transistor that is coupled to the input stage, wherein the buffering transistor is formed on a substrate, and wherein the buffering transistor has a channel with a doping concentration that is approximately the same as the substrate.

Abstract: An electronic device is provided that includes a power-on-reset (POR) circuit. The POR circuit includes a trigger stage configured to change an output if a first power supply voltage level exceeds a threshold voltage level and a first inverter and a second inverter being cross-coupled. An output of the second inverter is the POR output of the power-up reset circuit. The output is coupled to the trigger stage for switching the trigger stage off in response to a change of a signal at the output of the second inverter. The first inverter is dimensioned to follow with a voltage level at an output an initially rising slope of the first power supply voltage level and the second inverter is dimensioned to keep a voltage level at an output at a second power supply voltage level during the initially rising slope of the first power supply voltage level.

Abstract: In applications that use fractional-N phase locked loops (PLLs), the use of spread spectrum clocking (SSC) to reduced electromagnetic interference (EMI) would be desirable, but conflicts can occur. Here, a circuit is provided that includes both fractional logic circuitry and spread spectrum logic circuitry. This logic circuitry operates in combination with a phase selector to generally ensure that the likelihood of conflicts (which can occur in conventional circuit) are reduced.

Abstract: A phase generator includes a phase-shift enable and disable signal generator connected to configuration bits at its first input and connected to a reset signal at its reset input for generating a control signal; the configuration bits corresponding to the phase shift desired. The phase generator includes a logic signal generation device connected at its control input to the output of the phase-shift enable and disable signal generator and connected to a reset signal at its reset input for providing a phase generating signal; and a feedback element connected between the output of the logic signal generation device and control input of the phase-shift enable and disable signal generator for providing controlled clock signal to the phase-shift enable and disable signal generator.

Abstract: A combined spread spectrum and fractional-N phase locked loop circuit comprises a chain of a reference clock divider, a phase-frequency detector, a charge pump with loop filter, a voltage controlled oscillator that provides multiple phase outputs, and a feedback loop from the multiple phase outputs of the voltage controlled oscillator to a feedback input of the phase-frequency detector. The feedback loop includes a phase selector, a feedback divider and a control block with an output controlling said phase selector to select a particular phase as an input to the feedback divider. The control block includes spread spectrum logic circuitry receiving an input from the output of the phase selector and providing a directional control output signal and a phase step control signal. The control block further includes fractional logic circuitry receiving an input from the output of the phase selector and providing a phase step control signal.