Abstract: An apparatus for enabling duty cycle locking at the rising/falling edge of the clock includes a counter that receives a gated input clock. A lock detector receives an input clock for generating control signals. An address decoder is connected to the counter for generating a set of selection signals. A first multiplexer includes select lines connected to receive the selection signals. A plurality of delay chains provide multiple output taps with a first delay chain connected to the first multiplexer. A second multiplexer is connected to one of the plurality of delay chains with its select lines being hard wired. A latch is connected to the output of the first multiplexer and the second multiplexer for providing the output.

Abstract: A digital delay locked loop architecture is independent of feedback delay (clock tree delay). The architecture employs a frequency detector circuit which monitors the frequency of the input clock and then sets a division factor for a reference clock used to control delay tap selection. In this way, the architecture can support a fast locking time, coarse tuning and fine-tuning.

Abstract: A programmable frequency divider capable of operating in a normal mode and a fractional mode divides the input clock frequency by any integer ‘N’ provided at the input. In the normal mode the input is divided by the integer ‘N’. The divided output signal has a 50% duty cycle if the input clock has a 50% duty cycle. In the fractional mode, fractional division can be achieved from dividing by 1.5 to dividing by 255.5 in steps of 0.5.

Abstract: An apparatus for enabling duty cycle locking at the rising/falling edge of the clock includes a counter that receives a gated input clock. A lock detector receives an input clock for generating control signals. An address decoder is connected to the counter for generating a set of selection signals. A first multiplexer includes select lines connected to receive the selection signals. A plurality of delay chains provide multiple output taps with a first delay chain connected to the first multiplexer. A second multiplexer is connected to one of the plurality of delay chains with its select lines being hard wired. A latch is connected to the output of the first multiplexer and the second multiplexer for providing the output.

Abstract: A phase generator includes a phase-shift enable and disable signal generator connected to configuration bits at its first input and connected to a reset signal at its reset input for generating a control signal; the configuration bits corresponding to the phase shift desired. The phase generator includes a logic signal generation device connected at its control input to the output of the phase-shift enable and disable signal generator and connected to a reset signal at its reset input for providing a phase generating signal; and a feedback element connected between the output of the logic signal generation device and control input of the phase-shift enable and disable signal generator for providing controlled clock signal to the phase-shift enable and disable signal generator.

Abstract: A programmable frequency divider capable of operating in a normal mode and a fractional mode divides the input clock frequency by any integer ‘N’ provided at the input. In the normal mode the input is divided by the integer ‘N’. The divided output signal has a 50% duty cycle if the input clock has a 50% duty cycle. In the fractional mode, fractional division can be achieved from dividing by 1.5 to dividing by 255.5 in steps of 0.5.

Abstract: A digital delay locked loop architecture is independent of feedback delay (clock tree delay). The architecture employs a frequency detector circuit which monitors the frequency of the input clock and then sets a division factor for a reference clock used to control delay tap selection. In this way, the architecture can support a fast locking time, coarse tuning and fine-tuning.