Abstract: An information handling system includes a plug-in connector interface and an accelerator module installed into the plug-in connector interface. The plug-in connector interface is located at a location on a printed circuit board of the information handling system. The information handling system instantiates a workload on a processor, and allocates a processing resource of the accelerator module to the workload based upon the plug-in connector interface being located at the location.

Abstract: An interface apparatus for installing memory modules to an information handling system includes a riser card and an adapter. The riser card includes a first card-edge connector on a first edge of the riser card, and a second card-edge connector on a second edge of the riser card. The first card-edge connector is associated with a first interface and the second card-edge connector is associated with a second interface. The adapter includes a first socket on a first side of the adapter, and a second socket on a second side of the adapter opposite to the first side. The first socket and the second socket are associated with the second interface. The first socket is configured to receive the second card-edge connector of the riser card. The second socket is configured to receive a memory module.

Abstract: Described herein are methods and compositions for treating MPS I (Hurler/Hurler-Scheie/Scheie Syndrome) by administering to the subject a composition comprising a iduronidase (IDUA) polynucleotide. In one aspect, provided is a method of reducing, delaying and/or eliminating one or more of the need for additional treatment procedures, the onset, progression and/or severity of symptoms in a subject with MPS I, by administering to the subject a composition comprising a iduronidase (IDUA) polynucleotide.

Abstract: An information handling system includes a printed circuit board (PCB) and an integrated circuit device. The integrated circuit device includes a substrate and a die that is bonded via a first surface of the die to a first surface of the substrate. The substrate includes a ball grid array (BGA) on the first surface of the substrate. The integrated circuit device is bonded to a first surface of the PCB via the BGA. The die is collocated with the cutout area.

Abstract: In one embodiment, a method for distributing power using a power distribution system includes: receiving, by a first power distribution end of a power conductor of the power distribution system, power from a power supply unit via a first cable coupled to the power supply unit, the first power distribution end coupled to a first connector, the first connector including a first power interface coupling the first power distribution end to the first cable, the power conductor contoured to removably couple to a heatsink of the information handling system; and providing, by a second power distribution end of the power conductor, the power to a component of the information handling system via a second cable coupled to the component, the second power distribution end coupled to a second connector, the second connector including a second power interface coupling the second power distribution end to the second cable.

Abstract: An information handling system may include a printed circuit board and a plurality of connectors each electrically and mechanically coupled to the printed circuit board, each connector of the plurality of connectors configured to receive a respective modular information handling resource in order to electrically couple, via electrically-conductive pins of such connector, the respective modular information handling resource to the printed circuit board. Each connector may include a body comprising electrically non-conductive material and including a receptacle formed therein for receiving a mating edge connector of the respective modular information handling resource, a bus bar comprising electrically conductive material, other than the electrically-conductive pins of such connector, disposed within or upon the body and extending through at least a portion of the body, and an electrical termination electrically coupled to the bus bar.

Abstract: The present invention relates to a tooth-borne guide plate, a mucosa-borne guide plate, a bone-borne guide plate, and preparation and application methods therefor. The method for preparing a tooth-borne guide plate comprises: a) bonding a radiopaque material to teeth, bonding the radiopaque material to the gingival mucosa or/and bonding the radiopaque material to other anatomical features; b) performing CBCT photography, and acquiring CBCT data with radiopaque material information; c) acquiring oral cavity surface STL data with radiopaque material information; d) matching the CBCT data with the STL data; e) determining the positions of an implant and a retention pin; f) generating a base guide plate; g) generating an in-place guide plate; h) generating an implant guide plate; and i) generating a repair guide plate.

Abstract: A method of selectively disabling power delivery to a group of memory devices of an information handling system, the method including performing an initialization of a first memory device and a second memory device of the memory devices; after performing the initialization of the memory devices, performing boot procedures at the first memory device and the second memory device; while performing the boot procedures at the first memory device and the second memory device, detecting a memory failure of the first memory device; in response to detecting the memory failure of the first memory device, providing a signal to a power management integrate circuit (PMIC) of the first memory device to disable power at the first memory device; and continuing the boot procedures at the second memory device.

Abstract: The present utility model relates to a composite guide plate, comprising a base guide plate (1) and an implant guide plate (7), or comprising a base guide plate (1) and a repair guide plate (10), or comprising a base guide plate (1), an implant guide plate (7) and a repair guide plate (10), wherein the base guide plate (1) is provided with a retention pin sleeve (2); the implant guide plate (7) is provided with an implant sleeve (8) and a retention pin sleeve fastener (5); the retention pin sleeve fastener (5) is fastened on the retention pin sleeve (2) to connect the implant guide plate (7) to the base guide plate (1); the repair guide plate (10) is provided with the retention pin sleeve fastener (5); and the retention pin sleeve fastener (5) is fastened on the retention pin sleeve (2) to connect the repair guide plate (10) to the base guide plate (1).

Abstract: In one embodiment, a method for distributing power using a power distribution system includes: receiving, by a first power distribution end of a power conductor of the power distribution system, power from a power supply unit via a first cable coupled to the power supply unit, the first power distribution end coupled to a first connector, the first connector including a first power interface coupling the first power distribution end to the first cable, the power conductor contoured to removably couple to a heatsink of the information handling system; and providing, by a second power distribution end of the power conductor, the power to a component of the information handling system via a second cable coupled to the component, the second power distribution end coupled to a second connector, the second connector including a second power interface coupling the second power distribution end to the second cable.

Abstract: An information handling system includes an identification resistor, calibration circuitry, and a system-on-a-chip (SOC). The SOC sets the calibration line to a first digital state to place the calibration circuitry in an inventory mode. While the calibration circuitry is in the inventory mode, the SOC determines an inventory amount of time to charge the capacitor to a voltage substantially equal to a threshold voltage. The SOC then sets the calibration line to a second digital state to place the calibration circuitry in a calibration mode. While the calibration circuitry is in the calibration mode, the SOC determines a calibration amount of time to charge the capacitor to the voltage substantially equal to the threshold voltage. The SOC determines a resistance of the identification resistor based on the inventory amount of time and the calibration amount of time. The SOC also determines bit strapping information corresponding to the determined resistance.

Abstract: A method of selectively disabling power delivery to a group of memory devices of an information handling system, the method including performing an initialization of a first memory device and a second memory device of the memory devices; after performing the initialization of the memory devices, performing boot procedures at the first memory device and the second memory device; while performing the boot procedures at the first memory device and the second memory device, detecting a memory failure of the first memory device; in response to detecting the memory failure of the first memory device, providing a signal to a power management integrate circuit (PMIC) of the first memory device to disable power at the first memory device; and continuing the boot procedures at the second memory device.

Abstract: In one embodiment, a method for increasing power efficiency for an information handling system includes: monitoring, by a host service, one or more performance metrics associated with a memory device of the information handling system, the memory device including a power controller communicably coupled to a management device via a side-band bus; predicting, by the host service, an energy requirement for the memory device based on the one or more performance metrics; generating, by the host service, a power configuration profile based on the energy requirement, the power configuration profile indicating one or more power controller parameters associated with the power controller; sending, by the host service, the power configuration profile to the management device; receiving, by the management device, the power configuration profile; and modifying, by the management device and via the side-band bus, the one or more power controller parameters based on the power configuration profile.

Abstract: An information handling system may include a battery, a circuit board, an enclosure, and a control circuit. The circuit board may include at least one electric component, a first electrically conductive pad, and a second electrically conductive pad in proximity to the first electrically conductive pad. The enclosure may be configured to house components of the information handling system including the battery and the circuit board, and the enclosure may include a first member, a second member configured to be mechanically coupled to the first member, and a mechanical component comprising conductive material and configured to electrically short the first electrically conductive pad to the second electrically conductive pad when the first member is mechanically coupled to the second member, and cause electrical isolation of the first electrically conductive pad from the second electrically conductive pad when the first member is mechanically decoupled from the second member.

Abstract: A static resistant fan apparatus, comprising: a conductive shaft; a first conductive fan blade connected to the conductive shaft and extending away from the conductive shaft; a second conductive fan blade connected to the conductive shaft and extending away from the conductive shaft opposite to the first conductive fan blade; a conductive support structure surrounding the conductive shaft, wherein an inner edge of the support structure is spaced apart from the conductive shaft a distance; and a conductive ground pass coupled between the conductive shaft and the support structure and spanning the distance, wherein the conductive shaft, the conductive support structure, and the conductive ground pass provide a path to ground for the first conductive and the second conductive fan blades.

Abstract: An information handling system may include a battery, a circuit board, an enclosure, and a control circuit. The circuit board may include at least one electric component, a first electrically conductive pad, and a second electrically conductive pad in proximity to the first electrically conductive pad. The enclosure may be configured to house components of the information handling system including the battery and the circuit board, and the enclosure may include a first member, a second member configured to be mechanically coupled to the first member, and a mechanical component comprising conductive material and configured to electrically short the first electrically conductive pad to the second electrically conductive pad when the first member is mechanically coupled to the second member, and cause electrical isolation of the first electrically conductive pad from the second electrically conductive pad when the first member is mechanically decoupled from the second member.

Abstract: An information handling system may include a printed circuit board and a plurality of connectors each electrically and mechanically coupled to the printed circuit board, each connector of the plurality of connectors configured to receive a respective modular information handling resource in order to electrically couple, via electrically-conductive pins of such connector, the respective modular information handling resource to the printed circuit board. Each connector may include a body comprising electrically non-conductive material and including a receptacle formed therein for receiving a mating edge connector of the respective modular information handling resource, a bus bar comprising electrically conductive material, other than the electrically-conductive pins of such connector, disposed within or upon the body and extending through at least a portion of the body, and an electrical termination electrically coupled to the bus bar.

Abstract: An information handling system includes a printed circuit board (PCB) and an integrated circuit device. The integrated circuit device includes a substrate and a die that is bonded via a first surface of the die to a first surface of the substrate. The substrate includes a ball grid array (BGA) on the first surface of the substrate. The integrated circuit device is bonded to a first surface of the PCB via the BGA. The die is collocated with the cutout area.

Abstract: In one embodiment, a method for increasing power efficiency for an information handling system includes: monitoring, by a host service, one or more performance metrics associated with a memory device of the information handling system, the memory device including a power controller communicably coupled to a management device via a side-band bus; predicting, by the host service, an energy requirement for the memory device based on the one or more performance metrics; generating, by the host service, a power configuration profile based on the energy requirement, the power configuration profile indicating one or more power controller parameters associated with the power controller; sending, by the host service, the power configuration profile to the management device; receiving, by the management device, the power configuration profile; and modifying, by the management device and via the side-band bus, the one or more power controller parameters based on the power configuration profile.

Abstract: An information handling system includes an identification resistor, calibration circuitry, and a system-on-a-chip (SOC). The SOC sets the calibration line to a first digital state to place the calibration circuitry in an inventory mode. While the calibration circuitry is in the inventory mode, the SOC determines an inventory amount of time to charge the capacitor to a voltage substantially equal to a threshold voltage. The SOC then sets the calibration line to a second digital state to place the calibration circuitry in a calibration mode. While the calibration circuitry is in the calibration mode, the SOC determines a calibration amount of time to charge the capacitor to the voltage substantially equal to the threshold voltage. The SOC determines a resistance of the identification resistor based on the inventory amount of time and the calibration amount of time. The SOC also determines bit strapping information corresponding to the determined resistance.