Abstract: An electronic device includes an one of aluminum gallium nitride, aluminum nitride, indium aluminum nitride, or indium aluminum gallium nitride back barrier layer over a buffer structure, a gallium nitride layer over the back barrier layer, a hetero-epitaxy structure over the gallium nitride layer, first and second transistors over the hetero-epitaxy structure, and a hole injector having a doped gallium nitride structure over the hetero-epitaxy structure and a conductive structure partially over the doped gallium nitride structure to inject holes to form a hole layer proximate an interface of the back barrier layer and the buffer structure to mitigate vertical electric field back gating effects for the first transistor.

Abstract: A Group III-V semiconductor device and a method of fabricating the same including an in-situ surface passivation layer. A two-stage cleaning process may be effectuated for cleaning a reactor chamber prior to growing one or more epitaxial layers and forming subsequent surface passivation layers, wherein a first cleaning process may involve a remotely generated plasma containing fluorine-based reactive species for removing SiXNY residual material accumulated in the reactor chamber and/or over any components disposed therein.

Abstract: An electronic device includes an one of aluminum gallium nitride, aluminum nitride, indium aluminum nitride, or indium aluminum gallium nitride back barrier layer over a buffer structure, a gallium nitride layer over the back barrier layer, a hetero-epitaxy structure over the gallium nitride layer, first and second transistors over the hetero-epitaxy structure, and a hole injector having a doped gallium nitride structure over the hetero-epitaxy structure and a conductive structure partially over the doped gallium nitride structure to inject holes to form a hole layer proximate an interface of the back barrier layer and the buffer structure to mitigate vertical electric field back gating effects for the first transistor.

Abstract: A semiconductor device is described herein. The semiconductor device comprises a silicon substrate layer. The semiconductor device comprises a first semiconductor layer comprising a gallium nitride layer, the first semiconductor layer disposed over the silicon substrate layer. The semiconductor device comprises a second semiconductor layer disposed on the first semiconductor layer, the second semiconductor layer comprising an aluminum gallium nitride layer. The semiconductor device comprises a first drain contact extending through the second semiconductor layer and extending into the first semiconductor layer.

Abstract: An electronic device includes an one of aluminum gallium nitride, aluminum nitride, indium aluminum nitride, or indium aluminum gallium nitride back barrier layer over a buffer structure, a gallium nitride layer over the back barrier layer, a hetero-epitaxy structure over the gallium nitride layer, first and second transistors over the hetero-epitaxy structure, and a hole injector having a doped gallium nitride structure over the hetero-epitaxy structure and a conductive structure partially over the doped gallium nitride structure to inject holes to form a hole layer proximate an interface of the back barrier layer and the buffer structure to mitigate vertical electric field back gating effects for the first transistor.

Abstract: A semiconductor device includes a GaN FET on a silicon substrate and a buffer layer of III-N semiconductor material, with a columnar region, a transition region surrounding the columnar region, and an inter-columnar region around the transition region. The columnar region is higher than the inter-columnar region. The GaN FET includes a gate of III-N semiconductor material with a thickness greater than twice the vertical range of the top surface of the buffer layer in the columnar region. A difference between the gate thickness over the columnar region and over the transition region is less than half of the vertical range of the top surface of the buffer layer in the columnar surface. The semiconductor device may be formed by forming a gate layer of III-N semiconductor material over the barrier layer by a gate MOVPE process using a carrier gas that includes zero to 40 percent hydrogen gas.

Abstract: A semiconductor device containing an enhancement mode GaN FET on a III-N layer stack includes a low-doped GaN layer, a barrier layer including aluminum over the low-doped GaN layer, a stressor layer including indium over the barrier layer, and a cap layer including aluminum over the stressor layer. A gate recess extends through the cap layer and the stressor layer, but not through the barrier layer. The semiconductor device is formed by forming the barrier layer with a high temperature MOCVD process, forming the stressor layer with a low temperature MOCVD process and forming the cap layer with a low temperature MOCVD process. The gate recess is formed by a two-step etch process including a first etch step to remove the cap layer, and a second etch step to remove the stressor layer.

Abstract: A semiconductor device containing an enhancement mode GaN FET on a III-N layer stack includes a low-doped GaN layer, a barrier layer including aluminum over the low-doped GaN layer, a stressor layer including indium over the barrier layer, and a cap layer including aluminum over the stressor layer. A gate recess extends through the cap layer and the stressor layer, but not through the barrier layer. The semiconductor device is formed by forming the barrier layer with a high temperature MOCVD process, forming the stressor layer with a low temperature MOCVD process and forming the cap layer with a low temperature MOCVD process. The gate recess is formed by a two-step etch process including a first etch step to remove the cap layer, and a second etch step to remove the stressor layer.

Abstract: In some examples, a gallium-based device comprises a substrate layer; a first group-III nitride layer supported by the substrate layer; a second group-III nitride layer supported by the first group-III nitride layer; a tunnel barrier layer supported by the second group-III nitride layer; a passivation layer supported by the tunnel barrier layer; and source, gate, and drain contact structures supported by the first group-III nitride layer.

Abstract: A method of fabricating an epitaxial stack for Group IIIA-N transistors includes depositing at least one Group IIIA-N buffer layer on a substrate in a deposition chamber of a deposition system. At least one Group IIIA-N cap layer is then deposited on the first Group IIIA-N buffer layer. During a cool down from the deposition temperature for the cap layer deposition the gas mixture supplied to the deposition chamber includes NH3 and at least one other gas, wherein the gas mixture provide an ambient in the deposition chamber that is non-etching with respect to the cap layer so that at a surface of the cap layer there is (i) a root mean square (rms) roughness of <10 ? and (ii) a pit density for pits greater than (>) 2 nm deep less than (<) 10 pits per square ?m with an average pit diameter less than (<) 0.05 ?m.

Abstract: Disclosed examples provide methods for fabricating an epitaxial layer stack for a gallium nitride transistor in an integrated circuit, including forming an aluminum nitride layer (AlN) on a substrate with a predetermined resistivity in a processing chamber, forming an aluminum gallium nitride layer (AlGaN) on the AlN layer in the processing chamber, forming a surface layer on the AlGaN layer in the processing chamber, and controlling the processing chamber temperature after forming the surface layer to cool the substrate and the formed layers at a controlled rate to control wafer bow.

Abstract: Disclosed examples provide methods for fabricating an epitaxial layer stack for a gallium nitride transistor in an integrated circuit, including forming an aluminum nitride layer (AlN) on a substrate with a predetermined resistivity in a processing chamber, forming an aluminum gallium nitride layer (AlGaN) on the AlN layer in the processing chamber, forming a surface layer on the AlGaN layer in the processing chamber, and controlling the processing chamber temperature after forming the surface layer to cool the substrate and the formed layers at a controlled rate to control wafer bow.

Abstract: A semiconductor device containing an enhancement mode GaN FET on a III-N layer stack includes a low-doped GaN layer, a barrier layer including aluminum over the low-doped GaN layer, a stressor layer including indium over the barrier layer, and a cap layer including aluminum over the stressor layer. A gate recess extends through the cap layer and the stressor layer, but not through the barrier layer. The semiconductor device is formed by forming the barrier layer with a high temperature MOCVD process, forming the stressor layer with a low temperature MOCVD process and forming the cap layer with a low temperature MOCVD process. The gate recess is formed by a two-step etch process including a first etch step to remove the cap layer, and a second etch step to remove the stressor layer.

Abstract: An ultraviolet light emitting semiconductor chip, its use in a LED, and methods of its fabrication are disclosed. The semiconductor chip can include a buffer layer of AlxGa1-xN, where 0<x?1 having a thickness from about 10 ?m to about 3 mm and defining apertures in the thickness of the buffer layer formed due to lateral overgrowth of the buffer layer over a grooved basal substrate. A n-junction LED layer overlying the buffer layer, a multiple quantum well LED layer overlying the n-junction LED layer, and a p-junction LED layer overlying the multiple quantum well LED layer are also included in the chip, where all of the LED layers comprise AlxGa1-xN, where 0<x?1.

Abstract: A method of fabricating a multi-layer epitaxial buffer layer stack for transistors includes depositing a buffer stack on a substrate. A first voided Group IIIA-N layer is deposited on the substrate, and a first essentially void-free Group IIIA-N layer is then deposited on the first voided Group IIIA-N layer. A first high roughness Group IIIA-N layer is deposited on the first essentially void-free Group IIIA-N layer, and a first essentially smooth Group IIIA-N layer is deposited on the first high roughness Group IIIA-N layer. At least one Group IIIA-N surface layer is then deposited on the first essentially smooth Group IIIA-N layer.

Abstract: A method of fabricating an epitaxial stack for Group IIIA-N transistors includes depositing at least one Group IIIA-N buffer layer on a substrate in a deposition chamber of a deposition system. At least one Group IIIA-N cap layer is then deposited on the first Group IIIA-N buffer layer. During a cool down from the deposition temperature for the cap layer deposition the gas mixture supplied to the deposition chamber includes NH3 and at least one other gas, wherein the gas mixture provide an ambient in the deposition chamber that is non-etching with respect to the cap layer so that at a surface of the cap layer there is (i) a room mean square (rms) roughness of <10 ? and (ii) a pit density for pits greater than (>) 2 nm deep less than (<) 10 pits per square ?m with an average pit diameter less than (<) 0.05 ?m.

Abstract: A method of fabricating a multi-layer epitaxial buffer layer stack for transistors includes depositing a buffer stack on a substrate. A first voided Group IIIA-N layer is deposited on the substrate, and a first essentially void-free Group IIIA-N layer is then deposited on the first voided Group IIIA-N layer. A first high roughness Group IIIA-N layer is deposited on the first essentially void-free Group IIIA-N layer, and a first essentially smooth Group IIIA-N layer is deposited on the first high roughness Group IIIA-N layer. At least one Group IIIA-N surface layer is then deposited on the first essentially smooth Group IIIA-N layer.

Abstract: A method of fabricating a multi-layer epitaxial buffer layer stack for transistors includes depositing a buffer stack on a substrate. A first voided Group IIIA-N layer is deposited on the substrate, and a first essentially void-free Group IIIA-N layer is then deposited on the first voided Group IIIA-N layer. A first high roughness Group IIIA-N layer is deposited on the first essentially void-free Group IIIA-N layer, and a first essentially smooth Group IIIA-N layer is deposited on the first high roughness Group IIIA-N layer. At least one Group IIIA-N surface layer is then deposited on the first essentially smooth Group IIIA-N layer.

Abstract: A semiconductor device containing an enhancement mode GaN FET on a III-N layer stack includes a low-doped GaN layer, a barrier layer including aluminum over the low-doped GaN layer, a stressor layer including indium over the barrier layer, and a cap layer including aluminum over the stressor layer. A gate recess extends through the cap layer and the stressor layer, but not through the barrier layer. The semiconductor device is formed by forming the barrier layer with a high temperature MOCVD process, forming the stressor layer with a low temperature MOCVD process and forming the cap layer with a low temperature MOCVD process. The gate recess is formed by a two-step etch process including a first etch step to remove the cap layer, and a second etch step to remove the stressor layer.

Abstract: An ultraviolet light emitting semiconductor chip, its use in a LED, and methods of its fabrication are disclosed. The semiconductor chip can include a buffer layer of AlxGa1-xN, where 0<x?1 having a thickness from about 10 ?m to about 3 mm and defining apertures in the thickness of the buffer layer formed due to lateral overgrowth of the buffer layer over a grooved basal substrate. A n-junction LED layer overlying the buffer layer, a multiple quantum well LED layer overlying the n-junction LED layer, and a p-junction LED layer overlying the multiple quantum well LED layer are also included in the chip, where all of the LED layers comprise AlxGa1-xN, where 0<x?1.