Patents by Inventor Qhalid Fareed

Qhalid Fareed has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20210242200
    Abstract: A semiconductor device containing an enhancement mode GaN FET on a III-N layer stack includes a low-doped GaN layer, a barrier layer including aluminum over the low-doped GaN layer, a stressor layer including indium over the barrier layer, and a cap layer including aluminum over the stressor layer. A gate recess extends through the cap layer and the stressor layer, but not through the barrier layer. The semiconductor device is formed by forming the barrier layer with a high temperature MOCVD process, forming the stressor layer with a low temperature MOCVD process and forming the cap layer with a low temperature MOCVD process. The gate recess is formed by a two-step etch process including a first etch step to remove the cap layer, and a second etch step to remove the stressor layer.
    Type: Application
    Filed: April 19, 2021
    Publication date: August 5, 2021
    Inventors: Qhalid Fareed, Naveen Tipirneni
  • Patent number: 11011515
    Abstract: A semiconductor device containing an enhancement mode GaN FET on a III-N layer stack includes a low-doped GaN layer, a barrier layer including aluminum over the low-doped GaN layer, a stressor layer including indium over the barrier layer, and a cap layer including aluminum over the stressor layer. A gate recess extends through the cap layer and the stressor layer, but not through the barrier layer. The semiconductor device is formed by forming the barrier layer with a high temperature MOCVD process, forming the stressor layer with a low temperature MOCVD process and forming the cap layer with a low temperature MOCVD process. The gate recess is formed by a two-step etch process including a first etch step to remove the cap layer, and a second etch step to remove the stressor layer.
    Type: Grant
    Filed: May 24, 2018
    Date of Patent: May 18, 2021
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Qhalid Fareed, Naveen Tipirneni
  • Publication number: 20200203520
    Abstract: In some examples, a gallium-based device comprises a substrate layer; a first group-III nitride layer supported by the substrate layer; a second group-III nitride layer supported by the first group-III nitride layer; a tunnel barrier layer supported by the second group-III nitride layer; a passivation layer supported by the tunnel barrier layer; and source, gate, and drain contact structures supported by the first group-III nitride layer.
    Type: Application
    Filed: December 20, 2018
    Publication date: June 25, 2020
    Inventors: Nicholas S. DELLAS, Qhalid Fareed Rangoon Sayeed
  • Patent number: 10529561
    Abstract: A method of fabricating an epitaxial stack for Group IIIA-N transistors includes depositing at least one Group IIIA-N buffer layer on a substrate in a deposition chamber of a deposition system. At least one Group IIIA-N cap layer is then deposited on the first Group IIIA-N buffer layer. During a cool down from the deposition temperature for the cap layer deposition the gas mixture supplied to the deposition chamber includes NH3 and at least one other gas, wherein the gas mixture provide an ambient in the deposition chamber that is non-etching with respect to the cap layer so that at a surface of the cap layer there is (i) a root mean square (rms) roughness of <10 ? and (ii) a pit density for pits greater than (>) 2 nm deep less than (<) 10 pits per square ?m with an average pit diameter less than (<) 0.05 ?m.
    Type: Grant
    Filed: December 28, 2015
    Date of Patent: January 7, 2020
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Asad Mahmood Haider, Qhalid Fareed
  • Publication number: 20190288089
    Abstract: Disclosed examples provide methods for fabricating an epitaxial layer stack for a gallium nitride transistor in an integrated circuit, including forming an aluminum nitride layer (AlN) on a substrate with a predetermined resistivity in a processing chamber, forming an aluminum gallium nitride layer (AlGaN) on the AlN layer in the processing chamber, forming a surface layer on the AlGaN layer in the processing chamber, and controlling the processing chamber temperature after forming the surface layer to cool the substrate and the formed layers at a controlled rate to control wafer bow.
    Type: Application
    Filed: December 13, 2017
    Publication date: September 19, 2019
    Applicant: Texas Instruments Incorporated
    Inventors: Qhalid Fareed, Asad Mahmood Haider
  • Publication number: 20190181240
    Abstract: Disclosed examples provide methods for fabricating an epitaxial layer stack for a gallium nitride transistor in an integrated circuit, including forming an aluminum nitride layer (AlN) on a substrate with a predetermined resistivity in a processing chamber, forming an aluminum gallium nitride layer (AlGaN) on the AlN layer in the processing chamber, forming a surface layer on the AlGaN layer in the processing chamber, and controlling the processing chamber temperature after forming the surface layer to cool the substrate and the formed layers at a controlled rate to control wafer bow.
    Type: Application
    Filed: December 13, 2017
    Publication date: June 13, 2019
    Applicant: Texas Instruments Incorporated
    Inventors: Qhalid Fareed, Asad Mahmood Haider
  • Publication number: 20180277535
    Abstract: A semiconductor device containing an enhancement mode GaN FET on a III-N layer stack includes a low-doped GaN layer, a barrier layer including aluminum over the low-doped GaN layer, a stressor layer including indium over the barrier layer, and a cap layer including aluminum over the stressor layer. A gate recess extends through the cap layer and the stressor layer, but not through the barrier layer. The semiconductor device is formed by forming the barrier layer with a high temperature MOCVD process, forming the stressor layer with a low temperature MOCVD process and forming the cap layer with a low temperature MOCVD process. The gate recess is formed by a two-step etch process including a first etch step to remove the cap layer, and a second etch step to remove the stressor layer.
    Type: Application
    Filed: May 24, 2018
    Publication date: September 27, 2018
    Inventors: Qhalid Fareed, Naveen Tipirneni
  • Patent number: 9985177
    Abstract: An ultraviolet light emitting semiconductor chip, its use in a LED, and methods of its fabrication are disclosed. The semiconductor chip can include a buffer layer of AlxGa1-xN, where 0<x?1 having a thickness from about 10 ?m to about 3 mm and defining apertures in the thickness of the buffer layer formed due to lateral overgrowth of the buffer layer over a grooved basal substrate. A n-junction LED layer overlying the buffer layer, a multiple quantum well LED layer overlying the n-junction LED layer, and a p-junction LED layer overlying the multiple quantum well LED layer are also included in the chip, where all of the LED layers comprise AlxGa1-xN, where 0<x?1.
    Type: Grant
    Filed: March 22, 2016
    Date of Patent: May 29, 2018
    Assignee: University of South Carolina
    Inventors: M. Asif Khan, Qhalid Fareed, Vinod Adivarahan
  • Patent number: 9847223
    Abstract: A method of fabricating a multi-layer epitaxial buffer layer stack for transistors includes depositing a buffer stack on a substrate. A first voided Group IIIA-N layer is deposited on the substrate, and a first essentially void-free Group IIIA-N layer is then deposited on the first voided Group IIIA-N layer. A first high roughness Group IIIA-N layer is deposited on the first essentially void-free Group IIIA-N layer, and a first essentially smooth Group IIIA-N layer is deposited on the first high roughness Group IIIA-N layer. At least one Group IIIA-N surface layer is then deposited on the first essentially smooth Group IIIA-N layer.
    Type: Grant
    Filed: January 24, 2017
    Date of Patent: December 19, 2017
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Qhalid Fareed, Asad Mahmood Haider
  • Publication number: 20170186859
    Abstract: A method of fabricating an epitaxial stack for Group IIIA-N transistors includes depositing at least one Group IIIA-N buffer layer on a substrate in a deposition chamber of a deposition system. At least one Group IIIA-N cap layer is then deposited on the first Group IIIA-N buffer layer. During a cool down from the deposition temperature for the cap layer deposition the gas mixture supplied to the deposition chamber includes NH3 and at least one other gas, wherein the gas mixture provide an ambient in the deposition chamber that is non-etching with respect to the cap layer so that at a surface of the cap layer there is (i) a room mean square (rms) roughness of <10 ? and (ii) a pit density for pits greater than (>) 2 nm deep less than (<) 10 pits per square ?m with an average pit diameter less than (<) 0.05 ?m.
    Type: Application
    Filed: December 28, 2015
    Publication date: June 29, 2017
    Inventors: ASAD MAHMOOD HAIDER, QHALID FAREED
  • Publication number: 20170133221
    Abstract: A method of fabricating a multi-layer epitaxial buffer layer stack for transistors includes depositing a buffer stack on a substrate. A first voided Group IIIA-N layer is deposited on the substrate, and a first essentially void-free Group IIIA-N layer is then deposited on the first voided Group IIIA-N layer. A first high roughness Group IIIA-N layer is deposited on the first essentially void-free Group IIIA-N layer, and a first essentially smooth Group IIIA-N layer is deposited on the first high roughness Group IIIA-N layer. At least one Group IIIA-N surface layer is then deposited on the first essentially smooth Group IIIA-N layer.
    Type: Application
    Filed: January 24, 2017
    Publication date: May 11, 2017
    Inventors: Qhalid FAREED, Asad Mahmood HAIDER
  • Patent number: 9590086
    Abstract: A method of fabricating a multi-layer epitaxial buffer layer stack for transistors includes depositing a buffer stack on a substrate. A first voided Group IIIA-N layer is deposited on the substrate, and a first essentially void-free Group IIIA-N layer is then deposited on the first voided Group IIIA-N layer. A first high roughness Group IIIA-N layer is deposited on the first essentially void-free Group IIIA-N layer, and a first essentially smooth Group IIIA-N layer is deposited on the first high roughness Group IIIA-N layer. At least one Group IIIA-N surface layer is then deposited on the first essentially smooth Group IIIA-N layer.
    Type: Grant
    Filed: April 5, 2016
    Date of Patent: March 7, 2017
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Qhalid Fareed, Asad Mahmood Haider
  • Publication number: 20160293596
    Abstract: A semiconductor device containing an enhancement mode GaN FET on a III-N layer stack includes a low-doped GaN layer, a barrier layer including aluminum over the low-doped GaN layer, a stressor layer including indium over the barrier layer, and a cap layer including aluminum over the stressor layer. A gate recess extends through the cap layer and the stressor layer, but not through the barrier layer. The semiconductor device is formed by forming the barrier layer with a high temperature MOCVD process, forming the stressor layer with a low temperature MOCVD process and forming the cap layer with a low temperature MOCVD process. The gate recess is formed by a two-step etch process including a first etch step to remove the cap layer, and a second etch step to remove the stressor layer.
    Type: Application
    Filed: March 30, 2015
    Publication date: October 6, 2016
    Applicant: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Qhalid Fareed, Naveen Tipirneni
  • Publication number: 20160276533
    Abstract: An ultraviolet light emitting semiconductor chip, its use in a LED, and methods of its fabrication are disclosed. The semiconductor chip can include a buffer layer of AlxGa1-xN, where 0<x?1 having a thickness from about 10 ?m to about 3 mm and defining apertures in the thickness of the buffer layer formed due to lateral overgrowth of the buffer layer over a grooved basal substrate. A n-junction LED layer overlying the buffer layer, a multiple quantum well LED layer overlying the n-junction LED layer, and a p-junction LED layer overlying the multiple quantum well LED layer are also included in the chip, where all of the LED layers comprise AlxGa1-xN, where 0<x?1.
    Type: Application
    Filed: March 22, 2016
    Publication date: September 22, 2016
    Inventors: M. Asif Khan, Qhalid Fareed, Vinod Adivarahan
  • Publication number: 20160218202
    Abstract: A method of fabricating a multi-layer epitaxial buffer layer stack for transistors includes depositing a buffer stack on a substrate. A first voided Group IIIA-N layer is deposited on the substrate, and a first essentially void-free Group IIIA-N layer is then deposited on the first voided Group IIIA-N layer. A first high roughness Group IIIA-N layer is deposited on the first essentially void-free Group IIIA-N layer, and a first essentially smooth Group IIIA-N layer is deposited on the first high roughness Group IIIA-N layer. At least one Group IIIA-N surface layer is then deposited on the first essentially smooth Group IIIA-N layer.
    Type: Application
    Filed: April 5, 2016
    Publication date: July 28, 2016
    Inventors: Qhalid FAREED, Asad Mahmood HAIDER
  • Patent number: 9343563
    Abstract: Methods for forming a HEMT device are provided. The method includes forming an ultra-thin barrier layer on the plurality of thin film layers. A dielectric thin film layer is formed over a portion of the ultra-thin barrier layer to leave exposed areas of the ultra-thin barrier layer. A SAG S-D thin film layer is formed over the exposed areas of the ultra-thin barrier layer while leaving the dielectric thin film layer exposed. The dielectric thin film layer is then removed to expose the underlying ultra-thin barrier layer. The underlying ultra-thin barrier layer is treating with fluorine to form a treated area. A source and drain is added on the SAG S-D thin film layer, and a dielectric coating is deposited over the ultra-thin barrier layer treated with fluorine such that the dielectric coating is positioned between the source and the drain.
    Type: Grant
    Filed: August 4, 2014
    Date of Patent: May 17, 2016
    Assignee: University of South Carolina
    Inventors: Asif Khan, Qhalid Fareed, Vinod Adivarahan
  • Patent number: 9337023
    Abstract: A method of fabricating a multi-layer epitaxial buffer layer stack for transistors includes depositing a buffer stack on a substrate. A first voided Group IIIA-N layer is deposited on the substrate, and a first essentially void-free Group IIIA-N layer is then deposited on the first voided Group IIIA-N layer. A first high roughness Group IIIA-N layer is deposited on the first essentially void-free Group IIIA-N layer, and a first essentially smooth Group IIIA-N layer is deposited on the first high roughness Group IIIA-N layer. At least one Group IIIA-N surface layer is then deposited on the first essentially smooth Group IIIA-N layer.
    Type: Grant
    Filed: December 15, 2014
    Date of Patent: May 10, 2016
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Qhalid Fareed, Asad Mahmood Haider
  • Patent number: 9331240
    Abstract: An ultraviolet light emitting semiconductor chip, its use in a LED, and methods of its fabrication are disclosed. The semiconductor chip can include a buffer layer of AlxGa1-xN, where 0<x?1 having a thickness from about 10 ?m to about 3 mm and defining apertures in the thickness of the buffer layer formed due to lateral overgrowth of the buffer layer over a grooved basal substrate. A n-junction LED layer overlying the buffer layer, a multiple quantum well LED layer overlying the n-junction LED layer, and a p-junction LED layer overlying the multiple quantum well LED layer are also included in the chip, where all of the LED layers comprise AlxGa1-xN, where 0<x?1.
    Type: Grant
    Filed: June 8, 2009
    Date of Patent: May 3, 2016
    Assignee: University of South Carolina
    Inventors: M. Asif Khan, Qhalid Fareed, Vinod Adivarahan
  • Patent number: 9142714
    Abstract: An improved process for forming a UV emitting diode is described. The process includes providing a substrate. A super-lattice is formed directly on the substrate at a temperature of at least 800 to no more than 1,300° C. wherein the super-lattice comprises AlxInyGa1-x-yN wherein 0<x?1, 0?y?1 and 0<x+y?1. A first conductive layer with a first type of conductivity is formed on the super-lattice wherein the first conductive layer comprises AlxInyGa1-x-yN wherein 0<x?1, 0?y?1 and 0<x+y?1. A quantum well region is formed on the first conductive layer wherein the quantum well region comprises AlxInyGa1-x-yN wherein 0<x?1, 0?y?1 and 0<x+y?1. A second conductive layer is formed on the quantum well with a second type of conductivity wherein the second conductive layer comprises AlxInyGa1-x-yN wherein 0<x?1, 0?y?1 and 0<x+y?1.
    Type: Grant
    Filed: February 23, 2012
    Date of Patent: September 22, 2015
    Assignee: NITEK, INC.
    Inventors: Vinod Adivarahan, Qhalid Fareed, Asif Khan
  • Publication number: 20150001550
    Abstract: Methods for forming a HEMT device are provided. The method includes forming an ultra-thin barrier layer on the plurality of thin film layers. A dielectric thin film layer is formed over a portion of the ultra-thin barrier layer to leave exposed areas of the ultra-thin barrier layer. A SAG S-D thin film layer is formed over the exposed areas of the ultra-thin barrier layer while leaving the dielectric thin film layer exposed. The dielectric thin film layer is then removed to expose the underlying ultra-thin barrier layer. The underlying ultra-thin barrier layer is treating with fluorine to form a treated area. A source and drain is added on the SAG S-D thin film layer, and a dielectric coating is deposited over the ultra-thin barrier layer treated with fluorine such that the dielectric coating is positioned between the source and the drain.
    Type: Application
    Filed: August 4, 2014
    Publication date: January 1, 2015
    Inventors: Asif Khan, Qhalid Fareed, Vinod Adivarahan