Abstract: The present invention describes a method of forming a mask comprising: providing a substrate, the substrate having a first thickness; forming a balancing layer over the substrate, the balancing layer having a second thickness; forming an absorber layer over the balancing layer, the absorber layer having a first region separated from a second region by a third region; removing the absorber layer in the first region and the second region; removing the balancing layer in the second region; and reducing the substrate in the second region to a third thickness. The present invention also describes a mask comprising: an absorber layer, the absorber layer having a first opening and a second opening, the first opening uncovering a balancing layer disposed over a substrate having a first thickness, and the second opening uncovering the substrate having a second thickness.

Abstract: A method is described that involves accepting a mask design file input and then simulating the inspection of a mask through an optical channel. The mask design file has patterns. The optical channel corresponds to a mask inspection tool optical channel. The mask is patterned according to the mask design file patterns.

Abstract: The present invention describes a method of forming a mask comprising: providing a substrate, the substrate having a first thickness; forming a balancing layer over the substrate, the balancing layer having a second thickness; forming an absorber layer over the balancing layer, the absorber layer having a first region separated from a second region by a third region; removing the absorber layer in the first region and the second region; removing the balancing layer in the second region; and reducing the substrate in the second region to a third thickness. The present invention also describes a mask comprising: an absorber layers the absorber layer having a first opening and a second opening, the first opening uncovering a balancing layer disposed over a substrate having a first thickness, and the second opening uncovering the substrate having a second thickness.

Abstract: The present invention describes a method of forming a mask comprising: providing a substrate, the substrate having a first thickness; forming a balancing layer over the substrate, the balancing layer having a second thickness; forming an absorber layer over the balancing layer, the absorber layer having a first region separated from a second region by a third region; removing the absorber layer in the first region and the second region; removing the balancing layer in the second region; and reducing the substrate in the second region to a third thickness.

Abstract: The present invention describes a method of forming a mask comprising: providing a substrate, the substrate having a first thickness; forming a balancing layer over the substrate, the balancing layer having a second thickness; forming an absorber layer over the balancing layer, the absorber layer having a first region separated from a second region by a third region; removing the absorber layer in the first region and the second region; removing the balancing layer in the second region; and reducing the substrate in the second region to a third thickness.

Abstract: The present invention comprises a phase-shifting mask and a process for fabricating such a phase-shifting mask. The phase-shifting mask has trenches with vertical sidewall profiles which are retrograde. The retrograde profiles balance the transmission and phase of the light transmitted through the phase-shifted openings relative to the non-phase-shifted openings. The retrograde profile may be formed from an isotropic plasma etch.

Abstract: A method of fabricating minimum size and next-to-minimum size electrically conductive members using a litho-less process is disclosed. A substrate is provided, and a layer of gate dielectric material is formed on the substrate. A layer of electrically conductive material is formed over the gate dielectric material. A first mask is used to form a hard mask. A layer of first spacer material is deposited over the existing structures, and the layer of first spacer material is etched back to form spacers adjacent to the hard mask. The width of the first spacers determines the minimum size gate length. A layer of second spacer material is deposited over the existing structures, including the hard mask and first spacers. The layer of second spacer material is etched back to form a second set of spacers adjacent to the first spacers. The width of the first and second spacers together determine the next-to-minimum size gate length.

Abstract: A cascading transistor gate structure and method for fabricating the same are disclosed. A substrate is provided, and a layer of gate dielectric material is formed over the substrate. A layer of electrically conductive material is formed over the gate dielectric. A layer of hard mask material is formed on the layer of electrically conductive material. A photoresist mask is used to pattern the layer of hard mask material to form a hard mask. A layer of spacer material is deposited over the existing structures, and the layer of spacer material is etched to form a pair of spacers adjacent to the hard mask. The hard mask is removed, leaving the spacers. The layer of electrically conductive material is etched in alignment with the spacers. The spacers are then removed, revealing two transistor gates. A conductive region in formed in the substrate between the two gates. The two gates operate in tandem, yielding a cascading gate with an effective length that is the lengths of the two gates combined.

Abstract: A method of forming a narrow space using a litho-less process is disclosed. A first mask is formed on a substrate, the first mask having an edge. A spacer is then formed adjacent to the edge. A second mask is subsequently formed adjacent to the spacer. The spacer is then removed.

Abstract: A method and an apparatus for sensing quiescent current in a CMOS integrated circuit. The present invention utilizes circuitry which is not series coupled to the CMOS integrated circuit under test. The quiescent current, commonly referred to as I.sub.DDQ, flows through the supply line during the quiescent state of the CMOS integrated circuit. A magnetic field sensor is located on the substrate near the supply line of the CMOS integrated circuit. The magnetic field sensor detects the magnetic field generated from the supply line by I.sub.DDQ. The magnetic field sensor is coupled to output circuitry located on the substrate which produces a measurement result calibrated to indicate when I.sub.DDQ has a predetermined value.

Abstract: A phase-shifted reticle with patterns proximate each other having inverted phases for the features and phase-shifting elements, and method of fabricating the reticle. Each of the patterns and inverted patterns are structurally identical with regard to the direction of phase shift, so that any focal shift due to phase error is in the same direction for all patterns. In a preferred embodiment, the structurally identical inverted reticle is used to form an array of closely spaced contact or via openings. For a first pattern on the reticle, the feature will be the 0.degree. phase and the phase-shifting rim surrounding that feature will be the 180.degree. phase. All patterns surrounding the first pattern have phase-shifting rims of the 0.degree. phase and features of the 180.degree. phase. In this way, each pattern can form below conventional resolution features in the resist.

Abstract: A phase-shifted reticle with patterns proximate each other having inverted phases for the features and phase-shifting elements, and methods of fabricating the reticle. Each of the patterns and inverted patterns are structurally identical with regard to the direction of phase shift, so that any focal shift due to phase error is in the same direction for all patterns. In a preferred embodiment, the structurally identical inverted reticle is used to form an array of closely spaced contact or via openings. For a first pattern on the reticle, the feature will be the 0.degree. phase and the phase-shifting rim surrounding that feature will be the 180.degree. phase. All patterns surrounding the first pattern have phase-shifting rims of the 0.degree. phase and features of the 180.degree. phase. In this way, each pattern can form below conventional resolution features in the resist.