Patents by Inventor QIYANG HE
QIYANG HE has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20190315806Abstract: Provided are a polymyxin derivative having a general formula I structure, and a preparation method and an application thereof. The method for preparing the polymyxin derivative comprises the following steps: (1) an Fmoc-AA-OP side chain free amino group of a protected basic amino acid reacting with a halogenated resin to obtain an Fmoc-AA-OP-resin; (2) the Fmoc-AA-OP-resin being coupled one by one to obtain a linear peptide-resin; (3) the linear peptide-resin selectively removing a protective group, and carrying out solid-phase cyclization to obtain a cyclic peptide-resin; (4) the cyclic peptide-resin undergoing acidic hydrolysis and ether precipitation to obtain a crude product of a cyclic polypeptide; (5) the crude product being purified and/or salt transferred and lyophilized to obtain a pure product of the cyclic polypeptide.Type: ApplicationFiled: December 15, 2017Publication date: October 17, 2019Inventors: ALONG CUI, ZHUORONG LI, JIE JIN, YAN GAO, XINXIN HU, XUEFU YOU, YANG CHEN, QIYANG HE
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Patent number: 10159912Abstract: Methods of processing distillates, methods of removing at least some portion of total phosphorus in a distillate, methods of removing at least some portion of the soluble inorganic phosphorus, phytate phosphorus, or some combination thereof in a distillate, methods for obtaining phytate from distillates, methods for producing phytate derivatives and combinations thereof.Type: GrantFiled: May 6, 2016Date of Patent: December 25, 2018Assignee: REGENTS OF THE UNIVERSITY OF MINNESOTAInventors: Bo Hu, Qiyang He
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Patent number: 10090155Abstract: Various embodiments provide semiconductor devices. A base including a substrate and an interlayer dielectric layer is provided. The base has a first region and a second region that have an overlapped third region. A mask layer having a stacked structure is formed on the interlayer dielectric layer at the overlapped third region. Using the mask layer as an etching mask, the interlayer dielectric layer at the first region at both sides of the mask layer is etched, to expose the substrate and form a first contact via at the first region. Using the mask layer as an etching mask, the interlayer dielectric layer at the second region at both sides of the mask layer is etched, to form a second contact via at the second region. A conductive layer is formed to fill the first contact via and the second contact via.Type: GrantFiled: January 3, 2018Date of Patent: October 2, 2018Assignee: SEMICONDUCTOR MANUFACTURING INTERNATIONAL (SHANGHAI) CORPORATIONInventors: Qiyang He, Chenglong Zhang
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Patent number: 9892921Abstract: Various embodiments provide semiconductor devices and methods for forming the same. A base including a substrate and an interlayer dielectric layer is provided. The base has a first region and a second region that have an overlapped third region. A mask layer having a stacked structure is formed on the interlayer dielectric layer at the overlapped third region. Using the mask layer as an etching mask, the interlayer dielectric layer at the first region at both sides of the mask layer is etched, to expose the substrate and form a first contact via at the first region. Using the mask layer as an etching mask, the interlayer dielectric layer at the second region at both sides of the mask layer is etched, to form a second contact via at the second region. A conductive layer is formed to fill the first contact via and the second contact via.Type: GrantFiled: December 29, 2014Date of Patent: February 13, 2018Assignee: SEMICONDUCTOR MANUFACTURING INTERNATIONAL (SHANGHAI) CORPORATIONInventors: Qiyang He, Chenglong Zhang
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Patent number: 9633851Abstract: A method is provided for fabricating small pitch patterns. The method includes providing a semiconductor substrate, and forming a target material layer having a first region and a second region on the semiconductor substrate. The method also includes forming a plurality of discrete first sacrificial layers on the first region of the target material layer and a plurality of discrete second sacrificial layers on the second region of the target material layer, and forming first sidewall spacers on both sides of the discrete first sacrificial layers and the discrete second sacrificial layers. Further, the method includes removing the first sacrificial layers and the second sacrificial layers, and forming second sidewall spacers. Further, the method also includes forming discrete repeating patterns in the first region of the target material layer and a continuous pattern in the second region of the target material layer.Type: GrantFiled: March 1, 2016Date of Patent: April 25, 2017Assignee: SEMICONDUCTOR MANUFACTURING INTERNATIONAL CORP.Inventor: Qiyang He
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Patent number: 9541463Abstract: A capacitive pressure sensor is provided. The capacitive pressure sensor includes a substrate; and a first electrode formed in one surface of the substrate and vertical to the surface of the substrate. The capacitive pressure sensor also includes a second electrode with a portion facing the first sub-electrode, a portion facing the second sub-electrode and a portion formed in the other surface of the substrate. Further, the capacitive pressure sensor includes a first chamber between the first electrode and the second electrode and a second chamber formed in the second electrode. Further, the pressure sensor also includes a first sealing layer formed on the second electrode; and a second sealing layer formed on the other surface of the substrate.Type: GrantFiled: November 3, 2015Date of Patent: January 10, 2017Assignees: SEMICONDUCTOR MANUFACTURING INTERNATIONAL (BEIJING) CORPORATION, SEMICONDUCTOR MANUFACTURING INTERNATIONAL (SHANGHAI) CORPORATIONInventors: Qiyang He, Chenglong Zhang
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Publication number: 20160325205Abstract: Methods of processing distillates, methods of removing at least some portion of total phosphorus in a distillate, methods of removing at least some portion of the soluble inorganic phosphorus, phytate phosphorus, or some combination thereof in a distillate, methods for obtaining phytate from distillates, methods for producing phytate derivatives and combinations thereof.Type: ApplicationFiled: May 6, 2016Publication date: November 10, 2016Inventors: Bo Hu, Qiyang He
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Publication number: 20160181103Abstract: A method is provided for fabricating small pitch patterns. The method includes providing a semiconductor substrate, and forming a target material layer having a first region and a second region on the semiconductor substrate. The method also includes forming a plurality of discrete first sacrificial layers on the first region of the target material layer and a plurality of discrete second sacrificial layers on the second region of the target material layer, and forming first sidewall spacers on both sides of the discrete first sacrificial layers and the discrete second sacrificial layers. Further, the method includes removing the first sacrificial layers and the second sacrificial layers, and forming second sidewall spacers. Further, the method also includes forming discrete repeating patterns in the first region of the target material layer and a continuous pattern in the second region of the target material layer.Type: ApplicationFiled: March 1, 2016Publication date: June 23, 2016Inventor: QIYANG HE
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Patent number: 9349862Abstract: A method of fabricating a semiconductor device is provided. The method includes forming a gate having a first material on a substrate and a layer of a second material overlaying the gate. Sidewall spacers are formed on opposite sides of the gate. A characteristic of a portion of the substrate between adjacent sidewall spacers is changed using the layer of second material and the sidewall spacers as a mask. An isotropic wet etch process is performed to remove the substrate portion with a changed characteristic to form a recess in the substrate. An orientation selective wet etching process is performed on the recess to shape the inner walls of the recess into sigma-shape. Changing a substrate characteristic in conjunction with isotropic wet etching prevents the substrate from being damaged, and therefore can obtain defect free epitaxial SiGe growth performance.Type: GrantFiled: November 9, 2011Date of Patent: May 24, 2016Assignee: SEMICONDUCTOR MANUFACTURING INTERNATIONAL (BEIJING) CORPORATIONInventors: Yiying Zhang, Qiyang He
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Patent number: 9312328Abstract: A method is provided for fabricating small pitch patterns. The method includes providing a semiconductor substrate, and forming a target material layer having a first region and a second region on the semiconductor substrate. The method also includes forming a plurality of discrete first sacrificial layers on the first region of the target material layer and a plurality of discrete second sacrificial layers on the second region of the target material layer, and forming first sidewall spacers on both sides of the discrete first sacrificial layers and the discrete second sacrificial layers. Further, the method includes removing the first sacrificial layers and the second sacrificial layers, and forming second sidewall spacers. Further, the method also includes forming discrete repeating patterns in the first region of the target material layer and a continuous pattern in the second region of the target material layer.Type: GrantFiled: March 15, 2013Date of Patent: April 12, 2016Assignee: SEMICONDUCTOR MANUFACTURING INTERNATIONAL CORP.Inventor: Qiyang He
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Publication number: 20160054189Abstract: A capacitive pressure sensor is provided. The capacitive pressure sensor includes a substrate; and a first electrode formed in one surface of the substrate and vertical to the surface of the substrate. The capacitive pressure sensor also includes a second electrode with a portion facing the first sub-electrode, a portion facing the second sub-electrode and a portion formed in the other surface of the substrate. Further, the capacitive pressure sensor includes a first chamber between the first electrode and the second electrode and a second chamber formed in the second electrode. Further, the pressure sensor also includes a first sealing layer formed on the second electrode; and a second sealing layer formed on the other surface of the substrate.Type: ApplicationFiled: November 3, 2015Publication date: February 25, 2016Inventors: QIYANG HE, CHENGLONG ZHANG
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Patent number: 9207138Abstract: A capacitive pressure sensor is provided. The capacitive pressure sensor includes a substrate; and a first electrode formed in one surface of the substrate and vertical to the surface of the substrate. The capacitive pressure sensor also includes a second electrode with a portion facing the first sub-electrode, a portion facing the second sub-electrode and a portion formed in the other surface of the substrate. Further, the capacitive pressure sensor includes a first chamber between the first electrode and the second electrode and a second chamber formed in the second electrode. Further, the pressure sensor also includes a first sealing layer formed on the second electrode; and a second sealing layer formed on the other surface of the substrate.Type: GrantFiled: January 23, 2014Date of Patent: December 8, 2015Assignees: SEMICONDUCTOR MANUFACTURING INTERNATIONAL (BEIJING) CORPORATION, SEMICONDUCTOR MANUFACTURING INTERNATIONAL (SHANGHAI) CORPORATIONInventors: Qiyang He, Chenglong Zhang
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Publication number: 20150187601Abstract: Various embodiments provide semiconductor devices and methods for forming the same. A base including a substrate and an interlayer dielectric layer is provided. The base has a first region and a second region that have an overlapped third region. A mask layer having a stacked structure is formed on the interlayer dielectric layer at the overlapped third region. Using the mask layer as an etching mask, the interlayer dielectric layer at the first region at both sides of the mask layer is etched, to expose the substrate and form a first contact via at the first region. Using the mask layer as an etching mask, the interlayer dielectric layer at the second region at both sides of the mask layer is etched, to form a second contact via at the second region. A conductive layer is formed to fill the first contact via and the second contact via.Type: ApplicationFiled: December 29, 2014Publication date: July 2, 2015Inventors: QIYANG HE, CHENGLONG ZHANG
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Publication number: 20150061047Abstract: A capacitive pressure sensor is provided. The capacitive pressure sensor includes a substrate; and a first electrode formed in one surface of the substrate and vertical to the surface of the substrate. The capacitive pressure sensor also includes a second electrode with a portion facing the first sub-electrode, a portion facing the second sub-electrode and a portion formed in the other surface of the substrate. Further, the capacitive pressure sensor includes a first chamber between the first electrode and the second electrode and a second chamber formed in the second electrode. Further, the pressure sensor also includes a first sealing layer formed on the second electrode; and a second sealing layer formed on the other surface of the substrate.Type: ApplicationFiled: January 23, 2014Publication date: March 5, 2015Applicants: Semiconductor Manufacturing International (Shanghai) Corporation, SEMICONDUCTOR MANUFACTURING INTERNATIONAL (BEIJING) CORPORATIONInventors: QIYANG HE, CHENGLONG ZHANG
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Patent number: 8952297Abstract: This invention discloses a reaction apparatus for wafer treatment, an electrostatic chuck and a wafer temperature control method, in the field of semiconductor processing. The electrostatic chuck comprises an insulating layer for supporting a wafer and a lamp array disposed in the insulating layer. Each lamp of the lamp array can be independently controlled to turn on and off and/or to adjust the output power. By controlling the on/off switch and/or output power of each lamp of the lamp array the temperature of the wafer held on the ESC is adjusted and temperature non-uniformity can be more favorably adjusted, greatly improving wafer temperature uniformity, particularly alleviating non-radial temperature non-uniformity.Type: GrantFiled: January 17, 2012Date of Patent: February 10, 2015Assignee: Semiconductor Manufacturing International (Beijing) CorporationInventors: Qiyang He, Yiying Zhang
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Patent number: 8772148Abstract: A method is provided for fabricating a metal gate transistor. The method includes providing a semiconductor substrate; and forming a dielectric layer on the semiconductor substrate. The method also includes forming at least one dummy gate on the dielectric layer; and forming a first sidewall spacer around the dummy gate. Further, the method includes forming a gate dielectric layer with sidewalls protruding from sidewalls of the dummy gate and vertical to the semiconductor substrate by etching the dielectric layer using the first sidewall spacer and the dummy gate as an etching mask; and removing the dummy gate to form a trench. Further, the method also includes forming a metal gate in the trench; and forming a source region and a drain region in the semiconductor substrate.Type: GrantFiled: September 18, 2013Date of Patent: July 8, 2014Assignee: Semiconductor Manufacturing International (Shanghai) CorporationInventors: Xinpeng Wang, Qiyang He
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Patent number: 8759179Abstract: This disclosure relates to a method of forming a gate pattern and a semiconductor device. The gate pattern comprises a plurality of parallel gate bars, and each gate bar is broken up by gaps. The method comprises: making an etching characteristic of a gate material layer at least at positions where the gaps are to be formed different from that at remaining positions; forming a plurality of parallel openings in a second resist layer; performing a first etching process on the gate material layer with the second resist layer as a mask, wherein portions of the gate material layer at least at the positions where the gaps are to be formed are selectively left; and performing a second etching process on the gate material layer so as to selectively remove the portions. This method can more accurately control the shape and size of the gate pattern.Type: GrantFiled: September 23, 2011Date of Patent: June 24, 2014Assignee: Semiconductor Manufacturing International (Shanghai) CorporationInventors: Yiying Zhang, Qiyang He
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Patent number: 8741744Abstract: This disclosure is directed to a method of forming a gate pattern and a semiconductor device. The method comprises: providing a plurality of stacked structures which are parallel to each other and extend continuously in a first direction, and which are composed of a gate material bar and an etching barrier bar thereon; leaving second resist regions between gaps to be formed adjacent to each other across gate bars by a second photolithography process; selectively removing the etching barrier bars by a second etching process; forming a third resist layer having a plurality of openings parallel to each other and extending continuously in a second direction substantially perpendicular to the first direction by a third photolithography process; and forming the gate pattern by a third etching process. The method is capable of having a larger photolithography process window and better controlling the shape and size of a gate pattern.Type: GrantFiled: September 22, 2011Date of Patent: June 3, 2014Assignee: Semiconductor Manufacturing International (Shanghai) CorporationInventors: Qiyang He, Yiying Zhang
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Patent number: 8673707Abstract: A method for forming a metal gate includes providing a substrate, subsequently forming a dummy gate on the substrate, forming spacers on sidewalls of the dummy gate, forming a stop layer on the substrate, the dummy gate and spacers of the dummy gate, and forming a sacrificial dielectric layer on the dummy gate and the stop layer. The method further includes removing a part of the sacrificial dielectric layer and the stop layer until the dummy gate is exposed and, removing a residual sacrificial dielectric layer, depositing an interlayer dielectric layer on the dummy gate and the stop layer, polishing the interlayer dielectric layer until the dummy gate is exposed, removing the dummy gate to form a trench, and forming a metal gate in the trench. The interlayer dielectric layer is flat and substantially flush with the dummy gate, so that no recesses are formed thereon.Type: GrantFiled: August 4, 2011Date of Patent: March 18, 2014Assignee: Semiconductor Manufacturing International (Shanghai) CorporationInventors: Qiyang He, Yiying Zhang
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Patent number: 8507379Abstract: A semiconductor device and a manufacturing method thereof are disclosed. The method comprises: providing a substrate with a first dielectric layer and a gate, wherein the gate is embedded in the first dielectric layer and an upper portion of the gate is an exposed first metal; and covering only the exposed first metal with a conductive material that is harder to be oxidized than the first metal by a selective deposition. An advantage of the present invention is that the metal of the upper surface of the gate is prevented from being oxidized by covering the metal gate with the conductive material that is relatively harder to be oxidized, thereby facilitating the formation of an effective electrical connection to the gate.Type: GrantFiled: September 22, 2011Date of Patent: August 13, 2013Assignee: Semiconductor Manufacturing International (Beijing) CorporationInventors: Yiying Zhang, Qiyang He