Abstract: A method of fabricating an integrated circuit (IC) includes forming a metal interconnect stack on substrate that includes a plurality of product die each having a plurality of transistors connected together to implement a circuit function. The forming the metal interconnect stack includes depositing a metal interconnect layer comprising aluminum on a barrier layer at a first temperature. After depositing the metal interconnect layer, the metal interconnect stack is annealed in a non-oxidizing ambient at a maximum annealing temperature that is<the first temperature. After the annealing, a pattern is formed on the metal interconnect layer, and at least the metal interconnect layer is etched.

Abstract: A method of operating a computer system to improve via electromigration in an integrated circuit with multilevel interconnect. A method of operating a computer system to improve via electromigration in an integrated circuit with multilevel interconnect using via priority groups.

Abstract: A method of operating a computer system to improve via electromigration in an integrated circuit with multilevel interconnect. A method of operating a computer system to improve via electromigration in an integrated circuit with multilevel interconnect using via priority groups.

Abstract: A method of operating a computer system to improve via electromigration in an integrated circuit with multilevel interconnect. A method of operating a computer system to improve via electromigration in an integrated circuit with multilevel interconnect using via priority groups.

Abstract: A dual damascene process employs a via fill material (38) with an etch rate that is within 60% of an etch rate that an underlying dielectric layer (34) etches for a given dielectric etch chemistry in which a trench (48) and via (50) are being formed. In one embodiment, an organic via fill material plug (40) is employed in conjunction with a bottom anti-reflective coating (BARC) material layer (42). Both the organic via fill material plug (40) and the BARC material layer (42) are selected to have a material with an etch rate that within 60% of an etch rate that an underlying dielectric layer (34) etches for a given dielectric etch chemistry in which the trench (48) and via (50) are formed.

Abstract: A method of manufacturing an etch stop layer 18, 20, 21 on a semiconductor wafer 2 and the etch stop layer 18, 20, 21 produced by the method. The method includes depositing a dielectric layer 18, 20, 21 and applying a plasma treatment to the semiconductor wafer 2. Also, an etch stop layer 18, 20, 21 on a semiconductor wafer 2 having a modified surface and an amine deficient bulk.

Abstract: A method of manufacturing an etch stop layer 18, 20, 21 on a semiconductor wafer 2 and the etch stop layer 18, 20, 21 produced by the method. The method includes depositing a dielectric layer 18, 20, 21 and applying a plasma treatment to the semiconductor wafer 2. Also, an etch stop layer 18, 20, 21 on a semiconductor wafer 2 having a modified surface and an amine deficient bulk.

Abstract: A dual damascene process employs a via fill material (38) with an etch rate that is within 60% of an etch rate that an underlying dielectric layer (34) etches for a given dielectric etch chemistry in which a trench (48) and via (50) are being formed. In one embodiment, an organic via fill material plug (40) is employed in conjunction with a bottom anti-reflective coating (BARC) material layer (42). Both the organic via fill material plug (40) and the BARC material layer (42) are selected to have a material with an etch rate that within 60% of an etch rate that an underlying dielectric layer (34) etches for a given dielectric etch chemistry in which the trench (48) and via (50) are formed.

Abstract: Disclosed is a system for fabricating a semiconductor device (100). An interconnect structure (110) is formed on the semiconductor device (100) and a cap (112) is deposited over the interconnect structure (110). The interconnect structure (110) is annealed with the overlying cap (112) in place. The cap (112) is then removed after the interconnect structure (110) is annealed.

Abstract: Disclosed is a system for fabricating a semiconductor device (100). An interconnect structure (110) is formed on the semiconductor device (100) and a cap (112) is deposited over the interconnect structure (110). The interconnect structure (110) is annealed with the overlying cap (112) in place. The cap (112) is then removed after the interconnect structure (110) is annealed.

Abstract: An integrated circuit capacitor is formed by first forming a first dielectric layer (25) over a semiconductor (10). A copper structure (35) is formed in the first dielectric layer (25) and a second dielectric layer (80) is formed over the copper structure (35). A metal containing layer (90) is formed over the second dielectric layer (80) and the copper structure (35) and a planar surface is formed by removing portions of the metal containing layer (90) and the second dielectric layer (80).

Abstract: An embodiment of the invention is a method of manufacturing a semiconductor wafer 2 where a layer of undoped silicon glass 15 is formed over the front-end structure 3. Another embodiment of the present invention is an integrated circuit 2 having a back-end structure 4 in which the dielectric layer 15 contains undoped silicon glass.

Abstract: An embodiment of the invention is a method of manufacturing a semiconductor wafer 2 where a layer of undoped silicon glass 15 is formed over the front-end structure 3. Another embodiment of the present invention is an integrated circuit 2 having a back-end structure 4 in which the dielectric layer 15 contains undoped silicon glass.

Abstract: A polysilicon layer of a gate structure is covered by an implant blocking layer (e.g., silicon nitride). The implant blocking layer blocks introduction of implanted dopants while implanting an initial dose of first conductivity type dopant (e.g., for drain extension regions). The implant blocking layer is then removed and an additional dose of first conductivity type dopant in implanted to form the main source/drain regions. Then, metal is deposited and reacted to form a conductive silicide.

Abstract: A copper interconnect having a transition metal-nitride barrier (106) with a thin metal-silicon-nitride cap (108). A transition metal-nitride barrier (106) is formed over the structure. Then the barrier (106) is annealed in a Si-containing ambient to form a silicon-rich capping layer (108) at the surface of the barrier (106). The copper (110) is then deposited over the silicon-rich capping layer (108) with good adhesion.

Abstract: A method for fabricating a metal conductor in a semiconductor device includes forming a trench in a dielectric layer of the semiconductor device. The method also includes depositing a first conducting material within the trench to form a continuous liner layer within the trench. The liner layer is formed at a first predetermined temperature. The method further includes filling a remaining portion of the trench over the liner layer with a second conducting material at a second predetermined temperature. The second predetermined temperature is greater than the first predetermined temperature.

Abstract: An embodiment of the instant invention is a method of fabricating an electronic device over a semiconductor substrate having an interconnecting structure comprised of aluminum, the method comprising the steps of: forming a conductive structure (layers 120, 122 and 128 of FIGS. 1a-1d) comprised of a metal; forming a dielectric layer (layer 130 of FIGS. 1a-1d) over the conductive structure, the dielectric layer having an upper surface; forming an opening in the dielectric layer so as to expose a portion of the conductive structure, the opening having sidewalls; selectively depositing an aluminum-containing conductive material (material 136 and 137 of FIG. 1c) in the opening; and performing an etchback process so as to remove any of the aluminum-containing conductive material formed on the hardmask and so as to etchback any portion of the aluminum-containing conductor which is situated over the upper surface of the dielectric layer.

Abstract: Disclosed is a system for fabricating a semiconductor device (100). An interconnect structure (110) is formed on the semiconductor device (100) and a cap (112) is deposited over the interconnect structure (110). The interconnect structure (110) is annealed with the overlying cap (112) in place. The cap (112) is then removed after the interconnect structure (110) is annealed.

Abstract: A method of isolating an exposed conductive surface. An aluminum layer (130) is selectively formed over the exposed conductive (106) surface (e.g., Cu) but not over the surrounding dielectric (110) surface using a thermal CVD process. The aluminum layer (130) is then oxidized to form a thin isolating aluminum-oxide (108) over only the conductive surface. The isolating aluminum-oxide provides a barrier for the Cu while taking up minimal space and reducing the effective dielectric constant.

Abstract: A copper interconnect having a transition metal-nitride barrier (106) with a thin metal-silicon-nitride cap (108. A transition metal-nitride barrier (106) is formed over the structure. Then the barrier (106) is annealed in a Si-containing ambient to form a silicon-rich capping layer (108) at the surface of the barrier (106). The copper (110) is then deposited over the silicon-rich capping layer (108) with good adhesion.