Patents by Inventor Qian Fan

Qian Fan has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11954417
    Abstract: Disclosed a method for predicting permeability of a multi-mineral phase digital core based on deep learning. In the present disclosure, a three-dimensional digital core is constructed and a pore structure is randomly generated; after a plurality of multi-mineral digital core images is acquired by performing image segmentation on the three-dimensional digital core, permeability corresponding to each of the multi-mineral digital core images is acquired by simulation using multi-physics field simulation software and a multi-mineral digital core data set is constructed based on the plurality of multi-mineral digital core images and the permeability corresponding to each of the multi-mineral digital core images; an SE-ResNet18 convolutional neural network is constructed and trained with the multi-mineral digital core data set; and an image of a multi-mineral core to be predicted is input into the trained SE-ResNet18 convolutional neural network to determine the permeability of the multi-mineral core.
    Type: Grant
    Filed: November 8, 2023
    Date of Patent: April 9, 2024
    Assignee: CHINA UNIVERSITY OF PETROLEUM (EAST CHINA)
    Inventors: Hai Sun, Liang Zhou, Dongyan Fan, Lei Zhang, Jun Yao, Yongfei Yang, Kai Zhang, Qian Sang, Xia Yan, Lei Liu, Fei Luo, Yuda Kan
  • Patent number: 11918034
    Abstract: A device and method for preparing a fully granular cigarette/filter rod, and a prepared fully granular cigarette/filter rod are disclosed. In certain embodiments, negative pressure is used to adhere granular material onto a mesh-type conveyor belt. The granular material is preliminarily formed into fully granular cigarette/filter rod material by means of a pre-forming apparatus; the fully granular cigarette/filter rod material, traveling with the mesh-type conveyor belt, enters into a forming cavity, and undergoes heating and humidifying treatment, and a continuous solid porous substance is formed; the continuous solid porous substance is moved into the cooling/drying cavity, drying and cooling treatment are performed under the action of negative pressure, and a fully granular cigarette/filter rod with strong adhesion, porosity, permeability, and appropriate moisture is obtained.
    Type: Grant
    Filed: December 23, 2019
    Date of Patent: March 5, 2024
    Assignee: CHINA TOBACCO HUNAN INDUSTRIAL CO., LTD.
    Inventors: Yong Jin, Qian Chen, Ke Li, Hongmei Fan, Saibo Yu, Shitai Wang, Chao Tan, Haifeng Tan, Qi Liu
  • Publication number: 20240074294
    Abstract: A display module, including: a display panel; and a color film layer and a micro-lens layer, provided on a light-emitting side of the display panel; where, the color film layer includes a plurality of filter portions, and the micro-lens layer includes a plurality of first converging lenses and a plurality of second converging lenses; a gap is provided between two adjacent first converging lenses, and an orthographic projection of a first converging lens on the display panel is located within an orthographic projection of a filter portion on the display panel; a second converging lens is provided in the gap between two adjacent first converging lenses, and a vertex of the second converging lens is located between a vertex of the first converging lens and a bottom surface of the first converging lens.
    Type: Application
    Filed: September 7, 2022
    Publication date: February 29, 2024
    Inventors: Zhijian ZHU, Pengcheng LU, Shengji YANG, Kuanta HUANG, Xiaochuan CHEN, Qian WU, Longfei FAN, Dacheng ZHANG
  • Patent number: 11602243
    Abstract: The present disclosure provides a food processor, comprising: a cutter head, wherein a cutter is arranged on the cutter head, the intersecting line of the side wall of the cutter head and the cross section of the cutter head is a cutter head contour line, the maximum inscribed circle or the minimum circumscribed circle of the cutter head contour line is a cutter head base circle, and the central axis of the cutter head penetrates the center of the cutter head base circle; and a cup body arranged on the cutter head, wherein the intersecting line of the cup wall of the cup body and the cross section of the cup wall is a cup body contour line, the maximum inscribed circle or the minimum circumscribed circle of the cup body contour line is a cup body base circle.
    Type: Grant
    Filed: January 28, 2019
    Date of Patent: March 14, 2023
    Assignees: GUANGDONG MIDEA CONSUMER ELECTRICS MANUFACTURING CO., LTD., MIDEA GROUP CO., LTD.
    Inventors: Qian Fan, Xianghe Zeng, Jianfei Xu
  • Patent number: 11538963
    Abstract: A multilayer light emitting device having a plurality of low Si—H bonding dielectric layers is disclosed for improved p-GaN contact performance. Improved p-side contact resistance is provided using one or more bonding, via or passivation layers in a multilayer light emitting structure by the use of processes and dielectric materials and precursors that provide dielectric layers with a hydrogen content of less than 13 at. %.
    Type: Grant
    Filed: February 20, 2019
    Date of Patent: December 27, 2022
    Assignee: Ostendo Technologies, Inc.
    Inventors: Kameshwar Yadavalli, JeongHyuk Park, Gregory Batinica, Andrew Teren, Clarence Crouch, Qian Fan, Hussein S. El-Ghoroury
  • Patent number: 11532739
    Abstract: An integrated enhancement/depletion mode high electron mobility transistor (HEMT) includes a substrate, a buffer layer, a first barrier layer, a second barrier layer, a first source, a first drain a first gate, a second source, a second drain, and a second gate. The buffer layer is on the substrate. The first barrier layer is on the buffer layer, and the second barrier layer is on the first barrier layer. The second barrier layer covers a portion of the first barrier layer. The first source, the first drain, and the first gate are on the first barrier layer, and the second source, the second drain, and the second gate are on the second banner layer.
    Type: Grant
    Filed: August 4, 2020
    Date of Patent: December 20, 2022
    Assignee: SUZHOU HAN HUA SEMICONDUCTOR CO., LTD.
    Inventors: Xianfeng Ni, Qian Fan, Wei He
  • Patent number: 11495714
    Abstract: Solid state light emitting micropixels array structures having hydrogen barrier layers to minimize or eliminate undesirable passivation of doped GaN structures due to hydrogen diffusion.
    Type: Grant
    Filed: December 1, 2021
    Date of Patent: November 8, 2022
    Assignee: Ostendo Technologies, Inc.
    Inventors: Hussein El-Ghoroury, Kameshwar Yadavalli, Andrew Teren, Qian Fan
  • Patent number: 11476390
    Abstract: A III-V light emitting device with pixels (mesa regions) specifically designed to enable lower cost through layer vias is disclosed for reduced cost of manufacture of the device. Reduction of cost of manufacture is achieved by having non-uniform width trench regions formed during pixel etch for the multi-pixel array part of the device. Through-layer vias are specifically formed in the wider part of the trench regions using cheaper lithography toolset enabled by the larger via critical dimension achievable in the wider part of the trench regions (as compared to narrow part of the trench regions). Larger via critical dimension enables improved electrical (and consequently optical) performance of the device due to better overlay control as well as lower via resistance.
    Type: Grant
    Filed: January 28, 2021
    Date of Patent: October 18, 2022
    Assignee: Ostendo Technologies, Inc.
    Inventors: Hussein S. El-Ghoroury, Qian Fan, Kameshwar Yadavalli
  • Publication number: 20220090266
    Abstract: Solid state light emitting micropixels array structures having hydrogen barrier layers to minimize or eliminate undesirable passivation of doped GaN structures due to hydrogen diffusion.
    Type: Application
    Filed: December 1, 2021
    Publication date: March 24, 2022
    Applicant: Ostendo Technologies, Inc.
    Inventors: Hussein El-Ghoroury, Kameshwar Yadavalli, Andrew Teren, Qian Fan
  • Publication number: 20210384705
    Abstract: A method of fabricating vertical cavity surface emitting laser, comprising: providing a first substrate formed with a dielectric DBR and a first bonding layer, and a second substrate formed with a etch-stop layer, a heavily doped layer, an active region, a current-confinement layer, and an arsenide DBR firstly, then sticking a third substrate on the arsenide DBR, then removing the second substrate and the etch-stop layer, next bonding the heavily doped layer to the dielectric DBR, next removing the third substrate, finally forming a p-type electrode contact and an n-type electrode contact.
    Type: Application
    Filed: June 3, 2021
    Publication date: December 9, 2021
    Applicant: SUZHOU HANHUA SEMICONDUCTOR CO., LTD.
    Inventors: Qian Fan, Xianfeng Ni, Bin Hua, Ying Cui
  • Patent number: 11195975
    Abstract: Solid state light emitting micropixels array structures having hydrogen barrier layers to minimize or eliminate undesirable passivation of doped GaN structures due to hydrogen diffusion.
    Type: Grant
    Filed: June 6, 2019
    Date of Patent: December 7, 2021
    Assignee: Ostendo Technologies, Inc.
    Inventors: Hussein S. El-Ghoroury, Kameshwar Yadavalli, Andrew Teren, Qian Fan
  • Publication number: 20210318858
    Abstract: A method for monitoring a data chain comprises the steps of analyzing a source code to generate an abstract syntax tree, traversing the abstract syntax tree to obtain key nodes, and obtaining a data flow dependency relationship. A data chain is formed and graphically presented according to the data flow dependency relationship. The method further utilizes an interceptor to configure intercept points and key indicators at application programming interfaces of the source code, where the key indicators are graphically presented. An apparatus employing the method and a computer-readable storage medium storing the method is also disclosed.
    Type: Application
    Filed: May 27, 2020
    Publication date: October 14, 2021
    Inventors: QIAN-FAN XU, QI-MING LUO, LUNG-SHENG WANG
  • Publication number: 20210242372
    Abstract: A III-V light emitting device with pixels (mesa regions) specifically designed to enable lower cost through layer vias is disclosed for reduced cost of manufacture of the device. Reduction of cost of manufacture is achieved by having non-uniform width trench regions formed during pixel etch for the multi-pixel array part of the device. Through-layer vias are specifically formed in the wider part of the trench regions using cheaper lithography toolset enabled by the larger via critical dimension achievable in the wider part of the trench regions (as compared to narrow part of the trench regions). Larger via critical dimension enables improved electrical (and consequently optical) performance of the device due to better overlay control as well as lower via resistance.
    Type: Application
    Filed: January 28, 2021
    Publication date: August 5, 2021
    Inventors: Hussein S. El-Ghoroury, Qian Fan, Kameshwar Yadavalli
  • Patent number: 11056572
    Abstract: The present application provides a semiconductor device and a method for manufacturing the same. The method includes: sequentially forming a buffer layer and a barrier layer on a substrate, wherein a two-dimensional electron gas is formed between the buffer layer and the barrier layer; etching a source region and a drain region of the barrier layer to form a trench on the buffer layer, and doped layers are formed on the trench; forming a passivation layer on the barrier layer and the doped layers, and etching the passivation layer to expose a portion of the barrier layer, wherein the portion of the barrier layer is in contact with the doped layers; and doping ions into a portion of the buffer layer in contact with the portion of the buffer layer.
    Type: Grant
    Filed: March 3, 2020
    Date of Patent: July 6, 2021
    Assignee: SUZHOU HAN HUA SEMICONDUCTOR CO., LTD.
    Inventors: Xianfeng Ni, Qian Fan, Wei He
  • Patent number: 11049943
    Abstract: The present disclosure includes but is not limited to the III-Nitride semiconductor devices including a barrier layer, a gallium nitride or indium gallium nitride channel layer having a Ga-face coupled with the barrier layer, and a patterned thermoconductive layer having a thermal conductivity of at least 500 W/(m-K) within 1000 nanometers of a Ga-face of the gallium nitride channel layer. The semiconductor device may be a high-electron-mobility transistor or a semiconductor wafer. Methods for making the same also are described.
    Type: Grant
    Filed: December 21, 2018
    Date of Patent: June 29, 2021
    Assignee: SUZHOU HAN HUA SEMICONDUCTOR CO., LTD.
    Inventors: Xian-Feng Ni, Qian Fan, Wei He
  • Patent number: 11049952
    Abstract: An integrated enhancement/depletion mode high electron mobility transistor (HEMT) includes a substrate, a first buffer layer, a first barrier layer, a first channel layer, a first source, a first drain, a first gate, a second buffer layer, a second barrier layer, a second channel layer, a second source, a second drain, and a second gate. The first buffer layer is on the substrate. The first barrier layer is on a first area of the first buffer layer, the first channel layer is on the first barrier layer, and the first source, the first drain, and the first gate are on the first channel layer. The second buffer layer is on a second area of the first buffer layer, the second bather layer is on the second buffer layer, the second channel layer is on the second barrier layer, and the second source, the second drain, and the second gate are on the second channel layer.
    Type: Grant
    Filed: August 5, 2020
    Date of Patent: June 29, 2021
    Assignee: SUZHOU HAN HUA SEMICONDUCTOR CO., LTD.
    Inventors: Xianfeng Ni, Qian Fan, Wei He
  • Patent number: 11049718
    Abstract: The invention relates to a method to reduce the contact resistance of ohmic contact in group III-nitride high-electron mobility transistor (HEMT). A heavily n-type doped nitride layer with modulation doping is epitaxially grown on selected contact regions for use as ohmic contact layer. The method for producing the n++ ohmic contact layer includes at least the following: deposition of nitride HEMT epitaxial structure on substrates (such as SiC, silicon, sapphire, GaN etc), deposition in-situ or ex-situ mask for selective growth of n-contact, selective etching to create of openings within the mask layer, deposition of modulation doped n++ nitride ohmic contact layer followed by ohmic metal deposition. The modulation doping involves alternating epitaxy of high and low doped nitride layers with common n-type dopant such as Ge, Si etc. The modulation doping significantly increases the range of n-type doping without detrimental effect on the material quality of the contact layer.
    Type: Grant
    Filed: March 6, 2019
    Date of Patent: June 29, 2021
    Assignee: SUZHOU HAN HUA SEMICONDUCTOR CO., LTD.
    Inventors: Xian-Feng Ni, Qian Fan, Wei He
  • Patent number: 10879063
    Abstract: A method of fabricating a high-crystalline-quality and high-uniformity AlN layer within a high electron mobility transistor (HEMT) device with a metalorganic chemical vapor deposition (MOCVD) technique, includes: raising a temperature of a substrate to an ultra-high growth temperature; and supplying an Al source and an N source in pulses over the substrate under the ultra-high growth temperature, wherein the ultra-high growth temperature is at least 1300° C. At least for a first predetermined period of time in each cycle of the pulses, the Al source is switched on when the N source is switched off.
    Type: Grant
    Filed: June 12, 2019
    Date of Patent: December 29, 2020
    Assignee: SUZHOU HAN HUA SEMICONDUCTOR CO., LTD.
    Inventors: Xianfeng Ni, Qian Fan, Wei He
  • Publication number: 20200397190
    Abstract: A food processor, and a power supply board assembly and a base for a food processor. The power supply board assembly includes: a mounting bracket; a power supply board and a filter board, and the power supply board and the filter board are mounted at two opposite sides of the mounting bracket respectively, and the power supply board and the filter board are electrically connected with wires.
    Type: Application
    Filed: August 3, 2018
    Publication date: December 24, 2020
    Inventors: Guohua LUO, Qian FAN, Yunxiang LIU
  • Patent number: D946055
    Type: Grant
    Filed: July 10, 2020
    Date of Patent: March 15, 2022
    Inventor: Qian-Fan Zhang