Patents by Inventor Qian Fan

Qian Fan has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10438069
    Abstract: A method and an apparatus for detecting an abnormal situation are disclosed. The method includes detecting whether a first target exists in an obtained image; recognizing whether the first target holds an object, when the first target exists in the image; obtaining motion information of the object, when the first target holds the object; and determining, based on the motion information of the object, whether the abnormal situation exists.
    Type: Grant
    Filed: March 3, 2016
    Date of Patent: October 8, 2019
    Assignee: RICOH COMPANY, LTD.
    Inventors: Shengyin Fan, Zhongwei Cheng, Xin Wang, Qian Wang, Gang Qiao
  • Publication number: 20190304772
    Abstract: A method of fabricating a high-crystalline-quality and high-uniformity AlN layer within a high electron mobility transistor (HEMT) device with a metalorganic chemical vapor deposition (MOCVD) technique, includes: raising a temperature of a substrate to an ultra-high growth temperature; and supplying an Al source and an N source in pulses over the substrate under the ultra-high growth temperature, wherein the ultra-high growth temperature is at least 1300° C. At least for a first predetermined period of time in each cycle of the pulses, the Al source is switched on when the N source is switched off.
    Type: Application
    Filed: June 12, 2019
    Publication date: October 3, 2019
    Applicant: Suzhou Han Hua Semiconductor Co.,Ltd
    Inventors: Xianfeng NI, Qian FAN, Wei HE
  • Patent number: 10423271
    Abstract: A touch control armrest sleeve includes an body and a connecting portion. The body includes a flexible pad, a flexible touch panel and a protective cover. The connecting portion is connected to a first end and a second end of the body. The flexible touch panel includes a flexible substrate and a carbon nanotube touch function layer. The carbon nanotube touch function layer includes a carbon nanotube film, a plurality of first electrodes, and a plurality of second electrodes. The carbon nanotube film is located on the flexible substrate. The plurality of first electrodes and the plurality of second electrodes are electrically connected to the carbon nanotube film. A touch control seat incorporating such touch control armrest sleeve is also provided.
    Type: Grant
    Filed: March 14, 2017
    Date of Patent: September 24, 2019
    Assignees: Tsinghua University, HON HAI PRECISION INDUSTRY CO., LTD.
    Inventors: Shou-Shan Fan, Liang Liu, Li Qian, Yu-Quan Wang
  • Publication number: 20190264185
    Abstract: The present disclosure relates to a genetically engineered strain with high production of uridine and its construction method and application. The strain was constructed as follows: heterologously expressing pyrimidine nucleoside operon sequence pyrBCAKDFE (SEQ ID NO:1) on the genome of E coli prompted by strong promoter Ptrc to reconstruct the pathway of uridine synthesis; overexpressing the autologous prsA gene coding PRPP synthase by integration of another copy of prsA gene promoted by strong promoter Ptrc on the genome; deficiency of uridine kinase, uridine phosphorylase, ribonucleoside hydrolase, homoserine dehydrogenase I and ornithine carbamoyltransferase. When the bacteria was used for producing uridine, 40-67 g/L uridine could be obtained in a 5 L fermentator after fermentation for 40-70 h using the technical scheme provided by the discloure with the maximum productivity of 0.15-0.25 g uridine/g glucose and 1.
    Type: Application
    Filed: May 12, 2019
    Publication date: August 29, 2019
    Inventors: Xixian Xie, Ning Chen, Heyun Wu, Guoliang Li, Qiang Li, Xiaoguang Fan, Qingyang Xu, Chenglin Zhang, Yanjun Li, Qian Ma
  • Publication number: 20190267468
    Abstract: The present application provides a semiconductor device and a method for manufacturing the same. The method includes: sequentially forming a buffer layer and a barrier layer on a substrate, wherein a two-dimensional electron gas is formed between the buffer layer and the barrier layer; etching a source region and a drain region of the barrier layer to form a trench on the buffer layer, and doped layers are formed on the trench; forming a passivation layer on the barrier layer and the doped layers, and etching the passivation layer to expose a portion of the barrier layer, wherein the portion of the barrier layer is in contact with the doped layers; and doping ions into a portion of the buffer layer in contact with the portion of the buffer layer.
    Type: Application
    Filed: May 9, 2019
    Publication date: August 29, 2019
    Applicant: Suzhou Han Hua Semiconductor Co.,Ltd
    Inventors: Xianfeng NI, Qian FAN, Wei HE
  • Publication number: 20190267470
    Abstract: The present invention relates to a method for manufacturing a nitrogen-face polarity gallium nitride epitaxial structure, which includes: providing a gallium nitride template which includes a substrate and a first nitrogen-face polarity gallium nitride layer positioned on the substrate; re-growing the gallium nitride on a surface of the first nitrogen-face polarity gallium nitride layer to form a second nitrogen-face polarity gallium nitride layer; and sequentially growing a barrier layer and a channel layer on the second nitrogen-face polarity gallium nitride layer. The method for manufacturing the nitrogen-face polarity gallium nitride epitaxial structure provided by the present application enables a simple growth of the nitrogen-face polarity gallium nitride, can effectively eliminate the radio frequency dispersion phenomenon, and is beneficial to large-scale production and utilization of the nitrogen-face polarity gallium nitride epitaxial structure.
    Type: Application
    Filed: May 16, 2019
    Publication date: August 29, 2019
    Applicant: Suzhou Han Hua Semiconductor Co.,Ltd
    Inventors: Xianfeng NI, Qian FAN, Wei HE
  • Publication number: 20190267469
    Abstract: The present invention provides an integrated enhancement/depletion mode HEMT and a method for manufacturing the same, according to which an enhancement mode transistor and a depletion mode transistor can be integrated together, which is beneficial for increasing the application of gallium nitride HEMT devices and improving the characteristics of circuits, and lay a foundation for realizing monolithic integration of high-speed digital/analog mixed signal radio frequency circuits. At the same time, by utilizing the regrowth of the buffer layer and the doping requirements, electrons generated by impurities are made part of the doping layer, thus the doping concentration is improved while preventing excessive electrons from interfering with the devices.
    Type: Application
    Filed: May 16, 2019
    Publication date: August 29, 2019
    Applicant: Suzhou Han Hua Semiconductor Co.,Ltd
    Inventors: Xianfeng NI, Qian FAN, Wei HE
  • Publication number: 20190259865
    Abstract: The present invention provides an integrated enhancement/depletion mode HEMT and a method for manufacturing the same, by which method an enhancement mode transistor and a depletion mode transistor can be integrated together, which is beneficial for increasing the application of gallium nitride HEMT devices and improving the characteristics of circuits, and lay a foundation for realizing monolithic integration of high-speed digital/analog mixed signal radio frequency circuits. At the same time, by using a regrowth technology of a barrier layer, electrons generated by impurities are made part of a conductive channel, thus the concentration of the two-dimensional electron gas is increased, and the conductive performance is improved while preventing excessive electrons from interfering with the devices.
    Type: Application
    Filed: April 30, 2019
    Publication date: August 22, 2019
    Applicant: Suzhou Han Hua Semiconductor Co.,Ltd
    Inventors: Xianfeng NI, Qian FAN, Wei HE
  • Publication number: 20190150670
    Abstract: The present disclosure provides a food processor including a cutter head, on which a cutter is arranged; and a cup body arranged on the cutter head. The intersecting line of the side wall of the cutter head and the cross section of the cutter head is a cutter head contour line, the largest inscribed circle or the smallest circumscribed circle of the cutter head contour line is a cutter head base circle, and the central axis of the cutter head penetrates the center of the cutter head base circle. The intersecting line of the cup wall of the cup body and the cross section of the cup wall is a cup body contour line, the largest inscribed circle or the smallest circumscribed circle of the cup body contour line is a cup body base circle, and the central axis of the cup body penetrates the center of the cup body base circle.
    Type: Application
    Filed: January 28, 2019
    Publication date: May 23, 2019
    Inventors: Qian FAN, Xianghe Zeng, Jianfei Xu
  • Publication number: 20190150669
    Abstract: The present disclosure provides a food processor, comprising: a cutter head, wherein a cutter is arranged on the cutter head, the intersecting line of the side wall of the cutter head and the cross section of the cutter head is a cutter head contour line, the maximum inscribed circle or the minimum circumscribed circle of the cutter head contour line is a cutter head base circle, and the central axis of the cutter head penetrates the center of the cutter head base circle; and a cup body arranged on the cutter head, wherein the intersecting line of the cup wall of the cup body and the cross section of the cup wall is a cup body contour line, the maximum inscribed circle or the minimum circumscribed circle of the cup body contour line is a cup body base circle.
    Type: Application
    Filed: January 28, 2019
    Publication date: May 23, 2019
    Inventors: Qian FAN, Xianghe ZENG, Jianfei XU
  • Patent number: 10289254
    Abstract: A vehicle seat with touch control function includes a seat armrest, the seat armrest includes an armrest frame, a flexible pad, a flexible touch panel, and a protective cover. The flexible touch panel is elastic, and the flexible touch panel includes a flexible substrate and a carbon nanotube touch function layer to collect touch input from a user. Such flexible touch panel may be installed on or in armrest of any seat in vehicle, enabling control of a display while comfortably seated, having to lean forward is avoided. A vehicle-mounted entertainment system incorporating such touch control system is also provided.
    Type: Grant
    Filed: November 23, 2016
    Date of Patent: May 14, 2019
    Assignees: Tsinghua University, HON HAI PRECISION INDUSTRY CO., LTD.
    Inventors: Shou-Shan Fan, Liang Liu, Li Qian, Yu-Quan Wang
  • Patent number: 9978582
    Abstract: A method to improve the planarity of a semiconductor wafer and an assembly made from the method. In a preferred embodiment of the method, a compressive PECVD oxide layer such as SiO2 having a predetermined thickness or pattern is deposited on the second surface of a semiconductor wafer having an undesirable warp or bow. The thickness or pattern of the deposited oxide layer is determined by the measured warp or bow of the semiconductor wafer. The compressive oxide layer induces an offsetting compressive force on the second surface of the semiconductor wafer to reduce the warp and bow across the major surface of the semiconductor wafer.
    Type: Grant
    Filed: December 15, 2016
    Date of Patent: May 22, 2018
    Assignee: Ostendo Technologies, Inc.
    Inventors: Gregory Batinica, Kameshwar Yadavalli, Qian Fan, Benjamin A. Haskell, Hussein S. El-Ghoroury
  • Publication number: 20170178891
    Abstract: A method to improve the planarity of a semiconductor wafer and an assembly made from the method. In a preferred embodiment of the method, a compressive PECVD oxide layer such as SiO2 having a predetermined thickness or pattern is deposited on the second surface of a semiconductor wafer having an undesirable warp or bow. The thickness or pattern of the deposited oxide layer is determined by the measured warp or bow of the semiconductor wafer. The compressive oxide layer induces an offsetting compressive force on the second surface of the semiconductor wafer to reduce the warp and bow across the major surface of the semiconductor wafer.
    Type: Application
    Filed: December 15, 2016
    Publication date: June 22, 2017
    Inventors: Gregory Batinica, Kameshwar Yadavalli, Qian Fan, Benjamin A. Haskell, Hussein S. El-Ghoroury
  • Patent number: 9306116
    Abstract: Methods for bonding semiconductor wafers requiring the transfer of electrical and optical signals between the bonded wafers and across the bonding interface by interfusing optical interconnects on one wafer with optical interconnects on a second wafer, interfusing electrical interconnects on one wafer with electrical interconnects on the second wafer, and interfusing a dielectric intermediary bonding layer on one wafer with the dielectric intermediary bonding layer on the second wafer to bond the wafers together with electrical interconnections and optical interconnections between the wafers. The methods are also applicable to the bonding of semiconductor wafers to provide a high density of electrical interconnects between wafers.
    Type: Grant
    Filed: November 10, 2014
    Date of Patent: April 5, 2016
    Assignee: Ostendo Technologies, Inc.
    Inventors: Hussein S. El-Ghoroury, Chih-Li Chuang, Kameshwar Yadavalli, Qian Fan
  • Publication number: 20150072450
    Abstract: Methods for bonding semiconductor wafers requiring the transfer of electrical and optical signals between the bonded wafers and across the bonding interface. The methods for bonding of semiconductor wafers incorporate the formation of both electrical and optical interconnect vias within the wafer bonding interface to transfer electrical and optical signals between the bonded wafers. The electrical vias are formed across the bonding surface using multiplicity of metal posts each comprised of multiple layers of metal that are interfused across the bonding surface. The optical vias are formed across the bonding surface using multiplicity of optical waveguides each comprised of a dielectric material that interfuses across the bonding interface and having an index of refraction that is higher than the index of refraction of the dielectric intermediary bonding layer between the bonded wafers.
    Type: Application
    Filed: November 10, 2014
    Publication date: March 12, 2015
    Inventors: Hussein S. El-Ghoroury, Chih-Li Chuang, Kameshwar Yadavalli, Qian Fan
  • Patent number: 8912017
    Abstract: Methods for bonding semiconductor wafers requiring the transfer of electrical and optical signals between the bonded wafers and across the bonding interface. The methods incorporate the formation of both electrical and optical interconnect vias within the wafer bonding interface to transfer electrical and optical signals between the bonded wafers. The electrical vias are formed using multiplicity of metal posts each comprised of multiple layers of metal that are interfused across the bonding surface. The optical vias are formed using multiplicity of optical waveguides each comprised of a dielectric material that interfuses across the bonding interface and having an index of refraction that is higher than the index of refraction of the dielectric intermediary bonding layer between the bonded wafers. The electrical and optical vias are interspersed across the bonding surface between the bonded wafers to enable uniform transfer of both electrical and optical signals between the bonded wafers.
    Type: Grant
    Filed: May 3, 2012
    Date of Patent: December 16, 2014
    Assignee: Ostendo Technologies, Inc.
    Inventors: Hussein S. El-Ghoroury, Chih-Li Chuang, Kameshwar Yadavalli, Qian Fan
  • Publication number: 20120288995
    Abstract: Methods for bonding semiconductor wafers requiring the transfer of electrical and optical signals between the bonded wafers and across the bonding interface. The methods incorporate the formation of both electrical and optical interconnect vias within the wafer bonding interface to transfer electrical and optical signals between the bonded wafers. The electrical vias are formed across the bonding surface using multiplicity of metal posts that are interfused across the bonding surface. The optical vias are formed across the bonding surface using multiplicity of optical waveguides each comprised of a dielectric material that interfuses across the bonding interface and having an index of refraction that is higher than the index of refraction of the dielectric intermediary bonding layer between the bonded wafers. The electrical and optical vias are interspersed across the bonding surface between the bonded wafers to enable uniform transfer of both electrical and optical signals between the bonded wafers.
    Type: Application
    Filed: May 3, 2012
    Publication date: November 15, 2012
    Applicant: OSTENDO TECHNOLOGIES, INC.
    Inventors: Hussein S. El-Ghoroury, Chih-Li Chuang, Kameshwar Yadavalli, Qian Fan