Abstract: A 3D micro-curved epitaxial functional structure comprises a base layer that includes, from bottom to top, at least a sapphire substrate layer and a first epitaxial layer. A mask layer is located above the base layer, with spaced grooves that extend through it and expose the upper surface of the base layer. Multiple 3D micro-curved epitaxial structural units are formed, each with its bottom part filling a corresponding groove and its upper surface exhibiting a smooth 3D curved structure. Each 3D micro-curved epitaxial structural unit is partially in contact with the upper surface of the mask layer. By introducing an excess of Ga source while adjusting the crystal plane orientation angle during wet etching with Sc source, multiple epitaxial growth processes are performed to form the 3D micro-curved epitaxial functional structure, achieving compatibility with chip epitaxial processes and providing technical feasibility for creating complex structures.

Abstract: A method for fabricating a microlens array includes: step S1, providing a first substrate, and forming a patterned mask layer on the first substrate; step S2, etching the first substrate to form spaced grooves; step S3, removing the patterned mask layer; step S4, attaching a photoresist layer to the upper surface of the first substrate; step S5, softening the photoresist layer so that it adheres to the inner wall of the groove to form a concave smooth surface; step S6, solidifying the photoresist layer to form a working mold; applying an adhesive material and the working mold through the second substrate. The microlens array is produced by pressing the mold together or injecting PDMS material into the surface of the working mold.

Abstract: A method of fabricating vertical cavity surface emitting laser, comprising: providing a first substrate formed with a dielectric DBR and a first bonding layer, and a second substrate formed with a etch-stop layer, a heavily doped layer, an active region, a current-confinement layer, and an arsenide DBR firstly, then sticking a third substrate on the arsenide DBR, then removing the second substrate and the etch-stop layer, next bonding the heavily doped layer to the dielectric DBR, next removing the third substrate, finally forming a p-type electrode contact and an n-type electrode contact.

Abstract: A food processor, and a power supply board assembly and a base for a food processor. The power supply board assembly includes: a mounting bracket; a power supply board and a filter board, and the power supply board and the filter board are mounted at two opposite sides of the mounting bracket respectively, and the power supply board and the filter board are electrically connected with wires.

Abstract: The present disclosure provides a food processor, comprising: a cutter head, wherein a cutter is arranged on the cutter head, the intersecting line of the side wall of the cutter head and the cross section of the cutter head is a cutter head contour line, the maximum inscribed circle or the minimum circumscribed circle of the cutter head contour line is a cutter head base circle, and the central axis of the cutter head penetrates the center of the cutter head base circle; and a cup body arranged on the cutter head, wherein the intersecting line of the cup wall of the cup body and the cross section of the cup wall is a cup body contour line, the maximum inscribed circle or the minimum circumscribed circle of the cup body contour line is a cup body base circle.

Abstract: A multilayer light emitting device having a plurality of low Si—H bonding dielectric layers is disclosed for improved p-GaN contact performance. Improved p-side contact resistance is provided using one or more bonding, via or passivation layers in a multilayer light emitting structure by the use of processes and dielectric materials and precursors that provide dielectric layers with a hydrogen content of less than 13 at. %.

Abstract: An integrated enhancement/depletion mode high electron mobility transistor (HEMT) includes a substrate, a buffer layer, a first barrier layer, a second barrier layer, a first source, a first drain a first gate, a second source, a second drain, and a second gate. The buffer layer is on the substrate. The first barrier layer is on the buffer layer, and the second barrier layer is on the first barrier layer. The second barrier layer covers a portion of the first barrier layer. The first source, the first drain, and the first gate are on the first barrier layer, and the second source, the second drain, and the second gate are on the second banner layer.

Abstract: Solid state light emitting micropixels array structures having hydrogen barrier layers to minimize or eliminate undesirable passivation of doped GaN structures due to hydrogen diffusion.

Abstract: A III-V light emitting device with pixels (mesa regions) specifically designed to enable lower cost through layer vias is disclosed for reduced cost of manufacture of the device. Reduction of cost of manufacture is achieved by having non-uniform width trench regions formed during pixel etch for the multi-pixel array part of the device. Through-layer vias are specifically formed in the wider part of the trench regions using cheaper lithography toolset enabled by the larger via critical dimension achievable in the wider part of the trench regions (as compared to narrow part of the trench regions). Larger via critical dimension enables improved electrical (and consequently optical) performance of the device due to better overlay control as well as lower via resistance.

Abstract: Solid state light emitting micropixels array structures having hydrogen barrier layers to minimize or eliminate undesirable passivation of doped GaN structures due to hydrogen diffusion.

Abstract: A method of fabricating vertical cavity surface emitting laser, comprising: providing a first substrate formed with a dielectric DBR and a first bonding layer, and a second substrate formed with a etch-stop layer, a heavily doped layer, an active region, a current-confinement layer, and an arsenide DBR firstly, then sticking a third substrate on the arsenide DBR, then removing the second substrate and the etch-stop layer, next bonding the heavily doped layer to the dielectric DBR, next removing the third substrate, finally forming a p-type electrode contact and an n-type electrode contact.

Abstract: Solid state light emitting micropixels array structures having hydrogen barrier layers to minimize or eliminate undesirable passivation of doped GaN structures due to hydrogen diffusion.

Abstract: A method for monitoring a data chain comprises the steps of analyzing a source code to generate an abstract syntax tree, traversing the abstract syntax tree to obtain key nodes, and obtaining a data flow dependency relationship. A data chain is formed and graphically presented according to the data flow dependency relationship. The method further utilizes an interceptor to configure intercept points and key indicators at application programming interfaces of the source code, where the key indicators are graphically presented. An apparatus employing the method and a computer-readable storage medium storing the method is also disclosed.

Abstract: A III-V light emitting device with pixels (mesa regions) specifically designed to enable lower cost through layer vias is disclosed for reduced cost of manufacture of the device. Reduction of cost of manufacture is achieved by having non-uniform width trench regions formed during pixel etch for the multi-pixel array part of the device. Through-layer vias are specifically formed in the wider part of the trench regions using cheaper lithography toolset enabled by the larger via critical dimension achievable in the wider part of the trench regions (as compared to narrow part of the trench regions). Larger via critical dimension enables improved electrical (and consequently optical) performance of the device due to better overlay control as well as lower via resistance.

Abstract: The present application provides a semiconductor device and a method for manufacturing the same. The method includes: sequentially forming a buffer layer and a barrier layer on a substrate, wherein a two-dimensional electron gas is formed between the buffer layer and the barrier layer; etching a source region and a drain region of the barrier layer to form a trench on the buffer layer, and doped layers are formed on the trench; forming a passivation layer on the barrier layer and the doped layers, and etching the passivation layer to expose a portion of the barrier layer, wherein the portion of the barrier layer is in contact with the doped layers; and doping ions into a portion of the buffer layer in contact with the portion of the buffer layer.

Abstract: The present disclosure includes but is not limited to the III-Nitride semiconductor devices including a barrier layer, a gallium nitride or indium gallium nitride channel layer having a Ga-face coupled with the barrier layer, and a patterned thermoconductive layer having a thermal conductivity of at least 500 W/(m-K) within 1000 nanometers of a Ga-face of the gallium nitride channel layer. The semiconductor device may be a high-electron-mobility transistor or a semiconductor wafer. Methods for making the same also are described.

Abstract: An integrated enhancement/depletion mode high electron mobility transistor (HEMT) includes a substrate, a first buffer layer, a first barrier layer, a first channel layer, a first source, a first drain, a first gate, a second buffer layer, a second barrier layer, a second channel layer, a second source, a second drain, and a second gate. The first buffer layer is on the substrate. The first barrier layer is on a first area of the first buffer layer, the first channel layer is on the first barrier layer, and the first source, the first drain, and the first gate are on the first channel layer. The second buffer layer is on a second area of the first buffer layer, the second bather layer is on the second buffer layer, the second channel layer is on the second barrier layer, and the second source, the second drain, and the second gate are on the second channel layer.

Abstract: The invention relates to a method to reduce the contact resistance of ohmic contact in group III-nitride high-electron mobility transistor (HEMT). A heavily n-type doped nitride layer with modulation doping is epitaxially grown on selected contact regions for use as ohmic contact layer. The method for producing the n++ ohmic contact layer includes at least the following: deposition of nitride HEMT epitaxial structure on substrates (such as SiC, silicon, sapphire, GaN etc), deposition in-situ or ex-situ mask for selective growth of n-contact, selective etching to create of openings within the mask layer, deposition of modulation doped n++ nitride ohmic contact layer followed by ohmic metal deposition. The modulation doping involves alternating epitaxy of high and low doped nitride layers with common n-type dopant such as Ge, Si etc. The modulation doping significantly increases the range of n-type doping without detrimental effect on the material quality of the contact layer.

Abstract: A method of fabricating a high-crystalline-quality and high-uniformity AlN layer within a high electron mobility transistor (HEMT) device with a metalorganic chemical vapor deposition (MOCVD) technique, includes: raising a temperature of a substrate to an ultra-high growth temperature; and supplying an Al source and an N source in pulses over the substrate under the ultra-high growth temperature, wherein the ultra-high growth temperature is at least 1300° C. At least for a first predetermined period of time in each cycle of the pulses, the Al source is switched on when the N source is switched off.