Patents by Inventor Qianfan Xu
Qianfan Xu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 10645473Abstract: An all-optical network comprises: a first network; a second network; and a PWXC coupling the first network to the second network and comprising passive optical components. A method comprises: receiving a first optical signal from a first tail node of a first network; directing the first optical signal from a first input port of a PWXC to a first output port of the PWXC using first passive optical components; and transmitting the first optical signal to a third head node of a third network. An all-optical network comprising: a light bank; a first network coupled to the light bank; a second network coupled to the light bank; and a first PWXC coupling the first network and the second network.Type: GrantFiled: July 24, 2018Date of Patent: May 5, 2020Assignee: Futurewei Technologies, Inc.Inventors: Qianfan Xu, Feng Zhang, Xiao Andy Shen
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Patent number: 10641966Abstract: A free space coupling system comprising a waveguide horizontally positioned on an integrated circuit, and a silicon housing coupled to the waveguide, wherein the silicon housing comprises a reflective surface, a first port, wherein the first port is configured to receive light from an optic source positioned substantially parallel to the waveguide at a coupling point, and a second port, wherein the second port is oriented at about ninety degrees with respect to the first port, and wherein the second port is aligned with a grating port on the waveguide.Type: GrantFiled: March 20, 2017Date of Patent: May 5, 2020Assignee: Futurewei Technologies, Inc.Inventors: Rongsheng Miao, Zongrong Liu, Qianfan Xu, Xiao Shen
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Patent number: 10268056Abstract: An optical modulator comprises a silicon substrate, a buried oxide (BOX) layer disposed on top of the silicon substrate, and a ridge waveguide disposed on top of the BOX layer and comprising a first n-type silicon (n-Si) slab, a first gate oxide layer coupled to the first n-Si slab, a first p-type silicon (p-Si) slab coupled to the first gate oxide layer, and a light propagation path that travels sequentially through the first n-Si slab, the first gate oxide layer, and the first p-Si slab.Type: GrantFiled: June 1, 2017Date of Patent: April 23, 2019Assignee: Futurewei Technologies, Inc.Inventors: Dawei Zheng, Hongbing Lei, Qianfan Xu, Xiao Shen, Yu Sheng Bai
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Publication number: 20190058932Abstract: An all-optical network comprises: a first network; a second network; and a PWXC coupling the first network to the second network and comprising passive optical components. A method comprises: receiving a first optical signal from a first tail node of a first network; directing the first optical signal from a first input port of a PWXC to a first output port of the PWXC using first passive optical components; and transmitting the first optical signal to a third head node of a third network. An all-optical network comprising: a light bank; a first network coupled to the light bank; a second network coupled to the light bank; and a first PWXC coupling the first network and the second network.Type: ApplicationFiled: July 24, 2018Publication date: February 21, 2019Inventors: Qianfan Xu, Feng Zhang, Xiao Andy Shen
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Patent number: 10203454Abstract: A dense wavelength-division multiplexing (DWDM) optical network includes an optical input port configured to receive unmodulated optical signals from the optical fiber comprising wavelength channels; one or more modulators coupled to the optical input port wherein the one or more modulators are each configured to modulate a respective first wavelength channel of the wavelength channels with respective data to produce a modulated first wavelength channel when the modulator is in a transmit state; wherein an input optical power of each modulator is kept at substantially a first level and an output optical power of the each modulator is kept at substantially a second level during operation of the modulator. A method and an optical network node are also disclosed therein.Type: GrantFiled: May 31, 2017Date of Patent: February 12, 2019Assignee: Futurewei Technologies, Inc.Inventors: Tiangong Liu, Xiao Andy Shen, Qianfan Xu, Feng Zhang
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Patent number: 10133098Abstract: A metal-oxide semiconductor (MOS) optical modulator including a doped semiconductor layer having a waveguide structure, a dielectric layer disposed over the waveguide structure of the doped semiconductor layer, a gate region disposed over the dielectric layer, wherein the gate region comprises a transparent electrically conductive material having a refractive index lower than that of silicon, and a metal contact disposed over the gate region. The metal contact, the gate region, and the waveguide structure of the doped semiconductor layer may be vertically aligned with each other.Type: GrantFiled: April 17, 2015Date of Patent: November 20, 2018Assignee: Futurewei Technologies, Inc.Inventors: Hongmin Chen, Qianfan Xu, Li Yang, Xiao Shen, Dawei Zheng, Yusheng Bai, Hongbing Lei, Eric Dudley
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Patent number: 10120135Abstract: An apparatus comprises a substrate comprising a silicon dioxide (SiO2) material disposed on top of the substrate, a silicon waveguide comprising a first adiabatic tapering and enclosed in the silicon dioxide material, and a low-index waveguide disposed on top of the substrate and adjacent to the first adiabatic tapering. A mode converter fabrication method comprises obtaining a mode converter comprising a substrate, a silicon waveguide disposed on the substrate and comprising a sidewall and a first adiabatic tapering, and a hard mask disposed on the silicon waveguide and comprising a silicon dioxide layer, wherein the hard mask does not cover the sidewall, and oxidizing the silicon waveguide and the hard mask, wherein oxidizing the silicon waveguide and the hard mask encloses the silicon waveguide within the silicon dioxide layer.Type: GrantFiled: June 5, 2017Date of Patent: November 6, 2018Assignee: Futurewei Technologies, Inc.Inventors: Li Yang, Huapu Pan, Qianfan Xu, Dawei Zheng, Xiao Shen
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Patent number: 9933570Abstract: A method for fabricating a photonic integrated circuit (PIC) comprises providing a wafer comprising an insulator layer positioned between a top semiconductor layer and a base semiconductor layer, patterning the top semiconductor layer to simultaneously define a waveguide and a first etch mask window for forming a fiber-guiding v-groove that substantially aligns to an axis of optical signal propagation of the waveguide, removing a first portion of the top semiconductor layer to form the waveguide according to the patterning, removing a second portion of the top semiconductor layer to form the first etch mask window according to the patterning, and forming the fiber-guiding v-groove according to the first etch mask window.Type: GrantFiled: March 1, 2016Date of Patent: April 3, 2018Assignee: Futurewei Technologies, Inc.Inventors: Zongrong Liu, Qianfan Xu, Rongsheng Miao, Hongmin Chen, Xiao Shen, Yu Sheng Bai
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Patent number: 9838239Abstract: An apparatus comprising a first electrical driver configured to generate a first binary voltage signal according to first data, a second electrical driver configured to generate a second binary voltage signal according to second data, wherein the first data and the second data are different, and a first optical waveguide arm coupled to the first electrical driver and the second electrical driver, wherein the first optical waveguide arm is configured to shift a first phase of a first optical signal propagating along the first optical waveguide arm according to a first voltage difference between the first binary voltage signal and the second binary voltage signal to produce a first multi-level phase-shifted optical signal.Type: GrantFiled: January 7, 2016Date of Patent: December 5, 2017Assignee: Futurewei Technologies, Inc.Inventors: Morgan Chen, Qianfan Xu, Hungyi Lee, Yifan Gu, Liang Gu, Yen Dang, Gong Lei, Yuming Cao, Xiao Shen, Yu Sheng Bai
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Publication number: 20170346445Abstract: A dense wavelength-division multiplexing (DWDM) optical network comprises an optical bus, which includes an optical source configured to generate a plurality of unmodulated optical signals each having a different wavelength; an optical multiplexer configured to multiplex the unmodulated optical signals to produce a combined, unmodulated optical signal, and to transmit the combined, unmodulated optical signal through an optical fiber; a plurality of nodes connected in sequence to the output of the optical multiplexer. The plurality of nodes are connected by the optical fiber. A DWDM optical network and a method of operation of the DWDM optical network are also disclosed therein.Type: ApplicationFiled: May 31, 2017Publication date: November 30, 2017Applicant: Futurewei Technologies, Inc.Inventors: Xiao Andy SHEN, Qianfan XU, Feng ZHANG
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Patent number: 9823499Abstract: A metal-oxide-semiconductor (MOS) type semiconductor device, comprising a silicon substrate, a first cathode electrode and a second cathode electrode coupled to the silicon substrate and located on distal ends of the silicon substrate, a poly-silicon (Poly-Si) gate proximally located above the silicon substrate and between the first cathode electrode and the second cathode electrode, wherein the Poly-Si gate comprises a first post extending orthogonally relative to the silicon substrate comprising a first doped silicon slab, a second post extending orthogonally relative to the silicon substrate comprising a second doped silicon slab, wherein the second post is positioned so as to create a width between the first post and the second post, an anode electrode coupled to the first post and the second post and extending laterally from the first post to the second post, and a dielectric layer disposed between the first silicon substrate and the second silicon substrate.Type: GrantFiled: October 27, 2016Date of Patent: November 21, 2017Assignee: Futurewei Technologies, Inc.Inventors: Qianfan Xu, Xiao Shen, Hongmin Chen
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Publication number: 20170269302Abstract: An apparatus comprises a substrate comprising a silicon dioxide (SiO2) material disposed on top of the substrate, a silicon waveguide comprising a first adiabatic tapering and enclosed in the silicon dioxide material, and a low-index waveguide disposed on top of the substrate and adjacent to the first adiabatic tapering. A mode converter fabrication method comprises obtaining a mode converter comprising a substrate, a silicon waveguide disposed on the substrate and comprising a sidewall and a first adiabatic tapering, and a hard mask disposed on the silicon waveguide and comprising a silicon dioxide layer, wherein the hard mask does not cover the sidewall, and oxidizing the silicon waveguide and the hard mask, wherein oxidizing the silicon waveguide and the hard mask encloses the silicon waveguide within the silicon dioxide layer.Type: ApplicationFiled: June 5, 2017Publication date: September 21, 2017Inventors: Li Yang, Huapu Pan, Qianfan Xu, Dawei Zheng, Xiao Shen
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Publication number: 20170269392Abstract: An optical modulator comprises a silicon substrate, a buried oxide (BOX) layer disposed on top of the silicon substrate, and a ridge waveguide disposed on top of the BOX layer and comprising a first n-type silicon (n-Si) slab, a first gate oxide layer coupled to the first n-Si slab, a first p-type silicon (p-Si) slab coupled to the first gate oxide layer, and a light propagation path that travels sequentially through the first n-Si slab, the first gate oxide layer, and the first p-Si slab.Type: ApplicationFiled: June 1, 2017Publication date: September 21, 2017Inventors: Dawei Zheng, Hongbing Lei, Qianfan Xu, Xiao Shen, Yu Sheng Bai
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Publication number: 20170254954Abstract: A method for fabricating a photonic integrated circuit (PIC) comprises providing a wafer comprising an insulator layer positioned between a top semiconductor layer and a base semiconductor layer, patterning the top semiconductor layer to simultaneously define a waveguide and a first etch mask window for forming a fiber-guiding v-groove that substantially aligns to an axis of optical signal propagation of the waveguide, removing a first portion of the top semiconductor layer to form the waveguide according to the patterning, removing a second portion of the top semiconductor layer to form the first etch mask window according to the patterning, and forming the fiber-guiding v-groove according to the first etch mask window.Type: ApplicationFiled: March 1, 2016Publication date: September 7, 2017Inventors: Zongrong Liu, Qianfan Xu, Rongsheng Miao, Hongmin Chen, Xiao Shen, Yu Sheng Bai
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Patent number: 9709741Abstract: An apparatus comprises a substrate comprising a silicon dioxide (SiO2) material disposed on top of the substrate, a silicon waveguide comprising a first adiabatic tapering and enclosed in the silicon dioxide material, and a low-index waveguide disposed on top of the substrate and adjacent to the first adiabatic tapering. A mode converter fabrication method comprises obtaining a mode converter comprising a substrate, a silicon waveguide disposed on the substrate and comprising a sidewall and a first adiabatic tapering, and a hard mask disposed on the silicon waveguide and comprising a silicon dioxide (SiO2) layer, wherein the hard mask does not cover the sidewall, and oxidizing the silicon waveguide and the hard mask, wherein oxidizing the silicon waveguide and the hard mask encloses the silicon waveguide within the silicon dioxide layer.Type: GrantFiled: April 30, 2015Date of Patent: July 18, 2017Assignee: Futurewei Technologies, Inc.Inventors: Li Yang, Huapu Pan, Qianfan Xu, Dawei Zheng, Xiao Shen
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Publication number: 20170192175Abstract: A free space coupling system comprising a waveguide horizontally positioned on an integrated circuit, and a silicon housing coupled to the waveguide, wherein the silicon housing comprises a reflective surface, a first port, wherein the first port is configured to receive light from an optic source positioned substantially parallel to the waveguide at a coupling point, and a second port, wherein the second port is oriented at about ninety degrees with respect to the first port, and wherein the second port is aligned with a grating port on the waveguide.Type: ApplicationFiled: March 20, 2017Publication date: July 6, 2017Inventors: Rongsheng Miao, Zongrong Liu, Qianfan Xu, Xiao Shen
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Patent number: 9696567Abstract: An optical modulator comprises a silicon substrate, a buried oxide (BOX) layer disposed on top of the silicon substrate, and a ridge waveguide disposed on top of the BOX layer and comprising a first n-type silicon (n-Si) slab, a first gate oxide layer coupled to the first n-Si slab, a first p-type silicon (p-Si) slab coupled to the first gate oxide layer, and a light propagation path that travels sequentially through the first n-Si slab, the first gate oxide layer, and the first p-Si slab.Type: GrantFiled: January 26, 2015Date of Patent: July 4, 2017Assignee: Futurewei Technologies, Inc.Inventors: Dawei Zheng, Hongbing Lei, Qianfan Xu, Xiao Shen, Yusheng Bai
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Patent number: 9632281Abstract: A free space coupling system comprising a waveguide horizontally positioned on an integrated circuit, and a silicon housing coupled to the waveguide, wherein the silicon housing comprises a reflective surface, a first port, wherein the first port is configured to receive light from an optic source positioned substantially parallel to the waveguide at a coupling point, and a second port, wherein the second port is oriented at about ninety degrees with respect to the first port, and wherein the second port is aligned with a grating port on the waveguide.Type: GrantFiled: March 13, 2014Date of Patent: April 25, 2017Assignee: Futurewei Technologies, Inc.Inventors: Rongsheng Miao, Zongrong Liu, Qianfan Xu, Xiao Shen
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Publication number: 20170045761Abstract: A metal-oxide-semiconductor (MOS) type semiconductor device, comprising a silicon substrate, a first cathode electrode and a second cathode electrode coupled to the silicon substrate and located on distal ends of the silicon substrate, a poly-silicon (Poly-Si) gate proximally located above the silicon substrate and between the first cathode electrode and the second cathode electrode, wherein the Poly-Si gate comprises a first post extending orthogonally relative to the silicon substrate comprising a first doped silicon slab, a second post extending orthogonally relative to the silicon substrate comprising a second doped silicon slab, wherein the second post is positioned so as to create a width between the first post and the second post, an anode electrode coupled to the first post and the second post and extending laterally from the first post to the second post, and a dielectric layer disposed between the first silicon substrate and the second silicon substrate.Type: ApplicationFiled: October 27, 2016Publication date: February 16, 2017Inventors: Qianfan Xu, Xiao Shen, Hongmin Chen
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Patent number: 9523870Abstract: A silicon waveguide comprising a waveguide core that comprises a first positively doped (P1) region vertically adjacent to a second positively doped (P2) region. The P2 region is more heavily positively doped than the P1 region. A first negatively doped (N1) region is vertically adjacent to a second negatively doped (N2) region. The N2 region is more heavily negatively doped than the N1 region. The N2 region and the P2 region are positioned vertically adjacent to form a positive-negative (PN) junction. The N1 region, the N2 region, the P1 region, and the P2 region are positioned as a vertical PN junction and configured to completely deplete the P2 region of positive ions and completely deplete the N2 region of negative ions when a voltage drop is applied across the N1 region, the N2 region, the P1 region, and the P2 region.Type: GrantFiled: April 7, 2015Date of Patent: December 20, 2016Assignee: Futurewei Technologies, Inc.Inventors: Hongzhen Wei, Li Yang, Qianfan Xu, Xiao Shen