Patents by Inventor Qiang Guo

Qiang Guo has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 8209394
    Abstract: A device identifier (ID) is used across enterprise boundaries. A user can use the device ID to publish a device for sharing with other remote users. The remote users can discover devices that are shared by other users based on device IDs, connect to a selected device, and then verify that they have connected to the correct device based on its device ID. An account authority service may be used to manage the publication and/or discovery of the shared devices and their device IDs.
    Type: Grant
    Filed: June 2, 2008
    Date of Patent: June 26, 2012
    Assignee: Microsoft Corporation
    Inventors: Wei-Qiang Guo, Vaishali De, Rui Chen, Yordan Rouskov, Vikas Rajvanshy
  • Publication number: 20120153925
    Abstract: A voltage adjustment system includes a power supply for providing an initial voltage signal, a plurality of buck converters for receiving the initial voltage signal and generating one adjustable output voltage signal respectively, a microcontroller for determining one adjustable output voltage signal to output and determining whether a variable voltage signal generated by a buck converter that outputs the adjustable output voltage signal is positive or negative, a display unit for displaying value of the adjustable output voltage signal that is outputted, a plurality of voltage control units corresponding to the plurality of buck converters, and a voltage variation adjustment circuit including two buttons. The variable voltage signal is added to the adjustable output voltage signal generated by the same buck converter. Selection of the two buttons causes the microcontroller to adjust absolute value of the variable voltage signal generated by the buck converter through the corresponding voltage control unit.
    Type: Application
    Filed: April 15, 2011
    Publication date: June 21, 2012
    Applicants: HON HAI PRECISION INDUSTRY CO., LTD., HONG FU JIN PRECISION INDUSTRY (ShenZhen) CO., LTD .
    Inventors: LAN-YI FENG, QIANG GUO
  • Publication number: 20120137363
    Abstract: The disclosure provides a device and method for preventing CSRF attacks, in which the method comprises: intercepting request sent from a client browser to a server; generating a token; generating a response to the request; inserting the token into the response to the request; and sending the response to the request to the client browser with the token inserted into the response. With the method and device of the disclosure, it is assured that a token is inserted into all the requests made by a user through a client browser for accessing a resource. And it can be assured that the request is issued by the user himself by verifying whether the token in the request is valid, thereby preventing a CSRF attack.
    Type: Application
    Filed: November 29, 2011
    Publication date: May 31, 2012
    Applicant: IBM CORPORATION
    Inventors: Dikran S. Meliksetian, Gang Niu, Qiang Guo Tong
  • Publication number: 20110075925
    Abstract: A film scanning method is provided. When the film is judged as a negative film, the scanning device sets the scan exposure time for the film according to the base background color of the film. The negative film is scanned for the scan exposure time, wherein, the film passes through the scanning device at one time so as to complete the above judge of the film type and scanning of the film. The film scanning method automatically completes the recognition of film type, performs accurate scanning based on the scan exposure time, expands the dynamic range and reduces noise impacts, so as to obtain a scanned image with higher accuracy.
    Type: Application
    Filed: September 26, 2010
    Publication date: March 31, 2011
    Applicant: QISDA (SUZHOU) CO.,LTD
    Inventors: Xian-Qiang Guo, Chien-Hsing Tang
  • Publication number: 20110063692
    Abstract: A method of automatically identifying a scan region boundary, used for scanning a document under a non-unified background, includes: reading a reference linear scan data by a scanning device, the scanning device analyzing brightness values in each row of the reference linear scan data and determining a reference range value according to the brightness values in each row; and during scanning a document, the scanning device comparing brightness values of a linear scan data with the reference range value so as to determine the scan region boundary. The method confirms the scan boundary of a document and is not subjected to a backlight element or a document carrier. The method identifies the boundary of a document under a non-unified background, is applicable to scanning transparent and reflective documents and has strong resistance against environmental interference, not only simplifying the scanning device but also enhancing the automatic performance.
    Type: Application
    Filed: August 30, 2010
    Publication date: March 17, 2011
    Applicant: QISDA (SUZHOU) CO.,LTD
    Inventor: Xian-Qiang Guo
  • Publication number: 20110062976
    Abstract: The present invention discloses a pad structure and a method for testing a integrated circuit. The structure includes the first pads and the second pads, where the first pads are distributed over a peripheral portion of the integrated circuit and connected with lead-out wires of the integrated circuit, and the second pads are connected with a metal line at a circuit portion in the integrated circuit and are sized larger than the minimum characteristic dimension of the metal line and of the integrated circuit and smaller than the size of the first pads. The pad structure and method can position a test portion with improved efficiency. Correspondingly, a probe can be used to position the test portion with improved accuracy as well.
    Type: Application
    Filed: June 2, 2010
    Publication date: March 17, 2011
    Applicant: Semiconductor Manufacturing International (Shanghai) Corporation
    Inventors: Qiang Guo, Bin Gong
  • Publication number: 20110012613
    Abstract: The present invention discloses a failure detection method and a failure detection apparatus for detecting a defect in an electrical conductor. The failure detection method includes: providing at least two output terminals on the electrical conductor under test, the at least two output terminals having identical electric potentials; inputting a constant detection current sequentially to detection points arranged on the electrical conductor under test along a predetermined path; detecting an output current at one or more output terminals of the at least two output terminals; building a correspondence relationship between the detected one or more output currents at the one or more output terminals and positions of the detection points, based on information of the positions of the detection points and information of the detected one or more output currents at the one or more output terminals; and determining from the correspondence relationship whether the detection points have a defect.
    Type: Application
    Filed: July 14, 2010
    Publication date: January 20, 2011
    Applicant: Semiconductor Manufacturing International (Shanghai) Corporation
    Inventors: Bin Gong, Qiang Guo
  • Patent number: 7781895
    Abstract: An integration approach to improve electromigration resistance in a semiconductor device is described. A via hole is formed in a stack that includes an upper dielectric layer, a middle TiN ARC, and a lower first metal layer and is filled with a conformal diffusion barrier layer and a second metal layer. A key feature is that the etch process can be selected to vary the shape and location of the via bottom. A round or partially rounded bottom is formed in the first metal layer to reduce mechanical stress near the diffusion barrier layer. On the other hand, a flat bottom which stops on or in the TiN ARC is selected when exposure of the first metal layer to subsequent processing steps is a primary concern. Electromigration resistance is found to be lower than for a via structure with a flat bottom formed in a first metal layer.
    Type: Grant
    Filed: June 17, 2009
    Date of Patent: August 24, 2010
    Assignee: Chartered Semiconductor Manufacturing Ltd.
    Inventors: Bei Chao Zhang, Chun Hui Low, Hong Lim Lee, Sang Yee Loong, Qiang Guo
  • Patent number: 7691739
    Abstract: An integration approach to improve electromigration resistance in a semiconductor device is described. A via hole is formed in a stack that includes an upper dielectric layer, a middle TiN ARC, and a lower first metal layer and is filled with a conformal diffusion barrier layer and a second metal layer. A key feature is that the etch process can be selected to vary the shape and location of the via bottom. A round or partially rounded bottom is formed in the first metal layer to reduce mechanical stress near the diffusion barrier layer. On the other hand, a flat bottom which stops on or in the TiN ARC is selected when exposure of the first metal layer to subsequent processing steps is a primary concern. Electromigration resistance is found to be lower than for a via structure with a flat bottom formed in a first metal layer.
    Type: Grant
    Filed: March 13, 2006
    Date of Patent: April 6, 2010
    Assignee: Chartered Semiconductor Manufacturing Ltd.
    Inventors: Bei Chao Zhang, Chun Hui Low, Hong Lim Lee, Sang Yee Loong, Qiang Guo
  • Publication number: 20090320116
    Abstract: A federated realm discovery system within a federation determines a “home” realm associated with a portion of the user's credentials before the user's secret information (such as a password) is passed to a non-home realm. A login user interface accepts a user identifier and, based on the user identifier, can use various methods to identify an account authority service within the federation that can authenticate the user. In one method, a realm list of the user device can be used to direct the login to the appropriate home realm of the user. In another method, an account authority service in a non-home realm can look up the user's home realm and provide realm information directing the user device to login at the home realm.
    Type: Application
    Filed: June 19, 2008
    Publication date: December 24, 2009
    Applicant: Microsoft Corporation
    Inventors: Wei-Qiang Guo, Lynn Ayres, Rui Chen, Sarah Faulkner, Yordan Rouskov
  • Publication number: 20090320114
    Abstract: A federated realm discovery system within a federation determines a “home” realm associated with a portion of the user's credentials before the user's secret information (such as a password) is passed to a non-home realm. A login user interface accepts a user identifier and, based on the user identifier, can use various methods to identify an account authority service within the federation that can authenticate the user. In one method, a realm list of the user device can be used to direct the login to the appropriate home realm of the user. In another method, an account authority service in a non-home realm can look up the user's home realm and provide realm information directing the user device to login at the home realm.
    Type: Application
    Filed: June 19, 2008
    Publication date: December 24, 2009
    Applicant: MICROSOFT CORPORATION
    Inventors: Wei-Qiang Guo, Lynn Ayres, Rui Chen, Sarah Faulkner, Yordan Rouskov
  • Publication number: 20090250818
    Abstract: An integration approach to improve electromigration resistance in a semiconductor device is described. A via hole is formed in a stack that includes an upper dielectric layer, a middle TiN ARC, and a lower first metal layer and is filled with a conformal diffusion barrier layer and a second metal layer. A key feature is that the etch process can be selected to vary the shape and location of the via bottom. A round or partially rounded bottom is formed in the first metal layer to reduce mechanical stress near the diffusion barrier layer. On the other hand, a flat bottom which stops on or in the TiN ARC is selected when exposure of the first metal layer to subsequent processing steps is a primary concern. Electromigration resistance is found to be lower than for a via structure with a flat bottom formed in a first metal layer.
    Type: Application
    Filed: June 17, 2009
    Publication date: October 8, 2009
    Applicant: CHARTERED SEMICONDUCTOR MANUFACTURING LTD.
    Inventors: Bei Chao Zhang, Chun Hui Low, Hong Lim Lee, Sang Yee Loong, Qiang Guo
  • Publication number: 20090197076
    Abstract: In one aspect, the invention is an enamel composition comprising zinc oxide, diboron trioxide, zirconium dioxide, silicon oxide, sodium oxide, barium oxide, lithium oxide, at least one of aluminum oxide and aluminum oxide precursor compounds that form aluminum oxide upon sintering, and at least one of calcium oxide and calcium oxide precursor compounds that form calcium oxide upon sintering. In another aspect, the invention is a product coated with an enamel layer. In yet another aspect, the invention is a method of coating a product.
    Type: Application
    Filed: February 2, 2009
    Publication date: August 6, 2009
    Inventors: Lihua Xie, Jian Sun, Qiang Guo, Liang Chen
  • Patent number: 7486422
    Abstract: Methods and systems for recognizing a film in a scanner are provided. First, the film is previewed by the scanner to obtain an original preview image. The original preview image comprises a film image corresponding to the film. The original preview image also comprises pixels and each pixel has a first hue value, a second hue value, and a third hue value. The pixels with luminance in a predetermined range are then selected from the original preview image to acquire a second preview image. Next, the second preview image is framed according to the first hue values of the pixels to obtain an image frame. Finally, the image frame is sectioned to recognize the film image.
    Type: Grant
    Filed: September 7, 2004
    Date of Patent: February 3, 2009
    Assignee: Qisda Corporation
    Inventor: Xian-Qiang Guo
  • Publication number: 20070287284
    Abstract: A processing method for the metal surface in a dual damascene manufacturing is applied to a dual damascene semiconductor structure. The dual damascene semiconductor structure has a metal structure and a spin-on-dielectric (SOD) layer formed on the metal structure, wherein the SOD layer has at least one opening exposing a partial surface of the metal structure. Before the opening is filled, the monoxide on the exposed surface is first removed, then the exposed surface is treated by the plasma at an angle inclined to an axis perpendicular to the exposed surface. The processing method provided in the present invention can avoid the exposed surface being damaged by the plasma and improve the adhesion force between the exposed metal surface and the stuff.
    Type: Application
    Filed: June 7, 2006
    Publication date: December 13, 2007
    Inventor: Qiang Guo
  • Patent number: 7307016
    Abstract: A processing method for the metal surface in a dual damascene manufacturing is applied to a dual damascene semiconductor structure. The dual damascene semiconductor structure has a metal structure and a spin-on-dielectric (SOD) layer formed on the metal structure, wherein the SOD layer has at least one opening exposing a partial surface of the metal structure. Before the opening is filled, the monoxide on the exposed surface is first removed, then the exposed surface is treated by the plasma at an angle inclined to an axis perpendicular to the exposed surface. The processing method provided in the present invention can avoid the exposed surface being damaged by the plasma and improve the adhesion force between the exposed metal surface and the stuff.
    Type: Grant
    Filed: June 7, 2006
    Date of Patent: December 11, 2007
    Assignee: Grace Semiconductor Manufacturing Corporation
    Inventor: Qiang Guo
  • Patent number: 7175072
    Abstract: A transaction handling system and associated method are described for handling transactions based on a plurality of rule sets that apply to point sets (where the point sets contain points that can be consumed for goods and services, or have some other end-use connotation). Namely, the rule sets can be associated with respective point lots to define the characteristics and behavior of the respective point lots. For example, one rule in an applied rule set can determine whether a consumer is permitted to make a purchase without having sufficient points in the consumer's point lot, thus incurring a negative balance in the point lot. Another rule (e.g., a sandbox rule) can determine whether the consumer is permitted to use points only within a limited identified environment, or whether the consumer can use the points in any environment. An override rule set can override a default rule set on an individual account basis or on an individual consumer basis.
    Type: Grant
    Filed: March 25, 2005
    Date of Patent: February 13, 2007
    Assignee: Microsoft Corporation
    Inventors: Murali R. Krishnan, Neelamadhaba Mahapatro, Wei-Qiang Guo
  • Publication number: 20060238726
    Abstract: A method for scanning and processing a negative film used in a scanner is disclosed. The method includes scanning the negative film to generate an original image; performing a calibration algorithm on the original image according to a calibration curve; and performing a negative algorithm on the calibration image by using negative characteristic parameters of the standard scanner to generate a final image.
    Type: Application
    Filed: November 8, 2005
    Publication date: October 26, 2006
    Inventor: Xian-Qiang Guo
  • Publication number: 20060234498
    Abstract: The present invention provides a method of performing a surface treatment respectively on the via and the trench in a dual damascene process by the plasma having the inclined angle. The residual and/or the metal surface oxide on the bottom of the via are removed in the via and the trench etching process, and the surface treatment is performed on the surface of the trench, thereby preventing the poor electrical and increasing the adhesive force between the surface of the trench and the barrier metal layer, resulting in solving the disadvantage which the surface treatment can not be respectively performed and the trench according to the prior art.
    Type: Application
    Filed: April 18, 2005
    Publication date: October 19, 2006
    Inventor: Qiang Guo
  • Publication number: 20060213975
    Abstract: A transaction handling system and associated method are described for handling transactions based on a plurality of rule sets that apply to point sets (where the point sets contain points that can be consumed for goods and services, or have some other end-use connotation). Namely, the rule sets can be associated with respective point lots to define the characteristics and behavior of the respective point lots. For example, one rule in an applied rule set can determine whether a consumer is permitted to make a purchase without having sufficient points in the consumer's point lot, thus incurring a negative balance in the point lot. Another rule (e.g., a sandbox rule) can determine whether the consumer is permitted to use points only within a limited identified environment, or whether the consumer can use the points in any environment. An override rule set can override a default rule set on an individual account basis or on an individual consumer basis.
    Type: Application
    Filed: March 25, 2005
    Publication date: September 28, 2006
    Applicant: Microsoft Corporation
    Inventors: Murali Krishnan, Neelamadhaba Mahapatro, Wei-Qiang Guo