Patents by Inventor Qiang Guo

Qiang Guo has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20090250818
    Abstract: An integration approach to improve electromigration resistance in a semiconductor device is described. A via hole is formed in a stack that includes an upper dielectric layer, a middle TiN ARC, and a lower first metal layer and is filled with a conformal diffusion barrier layer and a second metal layer. A key feature is that the etch process can be selected to vary the shape and location of the via bottom. A round or partially rounded bottom is formed in the first metal layer to reduce mechanical stress near the diffusion barrier layer. On the other hand, a flat bottom which stops on or in the TiN ARC is selected when exposure of the first metal layer to subsequent processing steps is a primary concern. Electromigration resistance is found to be lower than for a via structure with a flat bottom formed in a first metal layer.
    Type: Application
    Filed: June 17, 2009
    Publication date: October 8, 2009
    Applicant: CHARTERED SEMICONDUCTOR MANUFACTURING LTD.
    Inventors: Bei Chao Zhang, Chun Hui Low, Hong Lim Lee, Sang Yee Loong, Qiang Guo
  • Publication number: 20090197076
    Abstract: In one aspect, the invention is an enamel composition comprising zinc oxide, diboron trioxide, zirconium dioxide, silicon oxide, sodium oxide, barium oxide, lithium oxide, at least one of aluminum oxide and aluminum oxide precursor compounds that form aluminum oxide upon sintering, and at least one of calcium oxide and calcium oxide precursor compounds that form calcium oxide upon sintering. In another aspect, the invention is a product coated with an enamel layer. In yet another aspect, the invention is a method of coating a product.
    Type: Application
    Filed: February 2, 2009
    Publication date: August 6, 2009
    Inventors: Lihua Xie, Jian Sun, Qiang Guo, Liang Chen
  • Patent number: 7486422
    Abstract: Methods and systems for recognizing a film in a scanner are provided. First, the film is previewed by the scanner to obtain an original preview image. The original preview image comprises a film image corresponding to the film. The original preview image also comprises pixels and each pixel has a first hue value, a second hue value, and a third hue value. The pixels with luminance in a predetermined range are then selected from the original preview image to acquire a second preview image. Next, the second preview image is framed according to the first hue values of the pixels to obtain an image frame. Finally, the image frame is sectioned to recognize the film image.
    Type: Grant
    Filed: September 7, 2004
    Date of Patent: February 3, 2009
    Assignee: Qisda Corporation
    Inventor: Xian-Qiang Guo
  • Publication number: 20070287284
    Abstract: A processing method for the metal surface in a dual damascene manufacturing is applied to a dual damascene semiconductor structure. The dual damascene semiconductor structure has a metal structure and a spin-on-dielectric (SOD) layer formed on the metal structure, wherein the SOD layer has at least one opening exposing a partial surface of the metal structure. Before the opening is filled, the monoxide on the exposed surface is first removed, then the exposed surface is treated by the plasma at an angle inclined to an axis perpendicular to the exposed surface. The processing method provided in the present invention can avoid the exposed surface being damaged by the plasma and improve the adhesion force between the exposed metal surface and the stuff.
    Type: Application
    Filed: June 7, 2006
    Publication date: December 13, 2007
    Inventor: Qiang Guo
  • Patent number: 7307016
    Abstract: A processing method for the metal surface in a dual damascene manufacturing is applied to a dual damascene semiconductor structure. The dual damascene semiconductor structure has a metal structure and a spin-on-dielectric (SOD) layer formed on the metal structure, wherein the SOD layer has at least one opening exposing a partial surface of the metal structure. Before the opening is filled, the monoxide on the exposed surface is first removed, then the exposed surface is treated by the plasma at an angle inclined to an axis perpendicular to the exposed surface. The processing method provided in the present invention can avoid the exposed surface being damaged by the plasma and improve the adhesion force between the exposed metal surface and the stuff.
    Type: Grant
    Filed: June 7, 2006
    Date of Patent: December 11, 2007
    Assignee: Grace Semiconductor Manufacturing Corporation
    Inventor: Qiang Guo
  • Patent number: 7175072
    Abstract: A transaction handling system and associated method are described for handling transactions based on a plurality of rule sets that apply to point sets (where the point sets contain points that can be consumed for goods and services, or have some other end-use connotation). Namely, the rule sets can be associated with respective point lots to define the characteristics and behavior of the respective point lots. For example, one rule in an applied rule set can determine whether a consumer is permitted to make a purchase without having sufficient points in the consumer's point lot, thus incurring a negative balance in the point lot. Another rule (e.g., a sandbox rule) can determine whether the consumer is permitted to use points only within a limited identified environment, or whether the consumer can use the points in any environment. An override rule set can override a default rule set on an individual account basis or on an individual consumer basis.
    Type: Grant
    Filed: March 25, 2005
    Date of Patent: February 13, 2007
    Assignee: Microsoft Corporation
    Inventors: Murali R. Krishnan, Neelamadhaba Mahapatro, Wei-Qiang Guo
  • Publication number: 20060238726
    Abstract: A method for scanning and processing a negative film used in a scanner is disclosed. The method includes scanning the negative film to generate an original image; performing a calibration algorithm on the original image according to a calibration curve; and performing a negative algorithm on the calibration image by using negative characteristic parameters of the standard scanner to generate a final image.
    Type: Application
    Filed: November 8, 2005
    Publication date: October 26, 2006
    Inventor: Xian-Qiang Guo
  • Publication number: 20060234498
    Abstract: The present invention provides a method of performing a surface treatment respectively on the via and the trench in a dual damascene process by the plasma having the inclined angle. The residual and/or the metal surface oxide on the bottom of the via are removed in the via and the trench etching process, and the surface treatment is performed on the surface of the trench, thereby preventing the poor electrical and increasing the adhesive force between the surface of the trench and the barrier metal layer, resulting in solving the disadvantage which the surface treatment can not be respectively performed and the trench according to the prior art.
    Type: Application
    Filed: April 18, 2005
    Publication date: October 19, 2006
    Inventor: Qiang Guo
  • Publication number: 20060213975
    Abstract: A transaction handling system and associated method are described for handling transactions based on a plurality of rule sets that apply to point sets (where the point sets contain points that can be consumed for goods and services, or have some other end-use connotation). Namely, the rule sets can be associated with respective point lots to define the characteristics and behavior of the respective point lots. For example, one rule in an applied rule set can determine whether a consumer is permitted to make a purchase without having sufficient points in the consumer's point lot, thus incurring a negative balance in the point lot. Another rule (e.g., a sandbox rule) can determine whether the consumer is permitted to use points only within a limited identified environment, or whether the consumer can use the points in any environment. An override rule set can override a default rule set on an individual account basis or on an individual consumer basis.
    Type: Application
    Filed: March 25, 2005
    Publication date: September 28, 2006
    Applicant: Microsoft Corporation
    Inventors: Murali Krishnan, Neelamadhaba Mahapatro, Wei-Qiang Guo
  • Publication number: 20060160354
    Abstract: An integration approach to improve electromigration resistance in a semiconductor device is described. A via hole is formed in a stack that includes an upper dielectric layer, a middle TiN ARC, and a lower first metal layer and is filled with a conformal diffusion barrier layer and a second metal layer. A key feature is that the etch process can be selected to vary the shape and location of the via bottom. A round or partially rounded bottom is formed in the first metal layer to reduce mechanical stress near the diffusion barrier layer. On the other hand, a flat bottom which stops on or in the TiN ARC is selected when exposure of the first metal layer to subsequent processing steps is a primary concern. Electromigration resistance is found to be lower than for a via structure with a flat bottom formed in a first metal layer.
    Type: Application
    Filed: March 14, 2006
    Publication date: July 20, 2006
    Applicant: Chartered Semiconductor Manufacturing Ltd.
    Inventors: BeiChao Zhang, Chun Low, Hong Lee, Sang Loong, Qiang Guo
  • Patent number: 7061966
    Abstract: A mobile wireless communications device and methods therefore, including receiving a signal (710), storing a portion of the received signal (730), identifying all possible pilot signals by determining slot boundary information for the stored signal portion (720), determining frame boundary information and/or scrambling code information (760) of the stored signal portion by correlating the stored signal portion with the scrambling codes based on the slot boundary information. In other embodiments, the search is performed in real-time without storing the signal.
    Type: Grant
    Filed: February 27, 2003
    Date of Patent: June 13, 2006
    Assignee: Motorola, Inc.
    Inventors: Brian Storm, Qiang Guo, Ming D. Tan, Xuping Zhou, Mang Zhu
  • Patent number: 7045455
    Abstract: An integration approach to improve electromigration resistance in a semiconductor device is described. A via hole is formed in a stack that includes an upper dielectric layer, a middle TiN ARC, and a lower first metal layer and is filled with a conformal diffusion barrier layer and a second metal layer. A key feature is that the etch process can be selected to vary the shape and location of the via bottom. A round or partially rounded bottom is formed in the first metal layer to reduce mechanical stress near the diffusion barrier layer. On the other hand, a flat bottom which stops on or in the TiN ARC is selected when exposure of the first metal layer to subsequent processing steps is a primary concern. Electromigration resistance is found to be lower than for a via structure with a flat bottom formed in a first metal layer.
    Type: Grant
    Filed: October 23, 2003
    Date of Patent: May 16, 2006
    Assignee: Chartered Semiconductor Manufacturing Ltd.
    Inventors: Beichao Zhang, Chun Hui Low, Hong Lim Lee, Sang Yee Loong, Qiang Guo
  • Patent number: 6913994
    Abstract: An improved method of forming a dual damascene structure that includes an organosilicate glass (OSG) dielectric layer is described. A via first process is followed in which a via is formed in the OSG layer and preferably stops on a SiC layer. The SiC layer is removed prior to stripping a photoresist containing the via pattern. A planarizing BARC layer is formed in the via to protect the exposed substrate from damage during trench formation. The method provides higher Kelvin via and via chain yields. Damage to the OSG layer at top corners of the via and trench is avoided. Furthermore, there is no pitting in the OSG layer at the trench bottom. Vertical sidewalls are achieved in the via and trench openings and via CD is maintained. The OSG loss during etching is minimized by removing the etch stop layer at an early stage of the dual damascene sequence.
    Type: Grant
    Filed: April 9, 2003
    Date of Patent: July 5, 2005
    Assignee: Agency for Science, Technology and Research
    Inventors: Qiang Guo, Ahila Krishnamoorthy, Xiaomei Bu, Vladimir N. Bliznetsov
  • Publication number: 20050063584
    Abstract: Methods and systems for recognizing a film in a scanner are provided. First, the film is previewed by the scanner to obtain an original preview image. The original preview image comprises a film image corresponding to the film. The original preview image also comprises pixels and each pixel has a first hue value, a second hue value, and a third hue value. The pixels with luminance in a predetermined range are then selected from the original preview image to acquire a second preview image. Next, the second preview image is framed according to the first hue values of the pixels to obtain an image frame. Finally, the image frame is sectioned to recognize the film image.
    Type: Application
    Filed: September 7, 2004
    Publication date: March 24, 2005
    Inventor: Xian-Qiang Guo
  • Publication number: 20040203223
    Abstract: An improved method of forming a dual damascene structure that includes an organosilicate glass (OSG) dielectric layer is described. A via first process is followed in which a via is formed in the OSG layer and preferably stops on a SiC layer. The SiC layer is removed prior to stripping a photoresist containing the via pattern. A planarizing BARC layer is formed in the via to protect the exposed substrate from damage during trench formation. The method provides higher Kelvin via and via chain yields. Damage to the OSG layer at top comers of the via and trench is avoided. Furthermore, there is no pitting in the OSG layer at the trench bottom. Vertical sidewalls are achieved in the via and trench openings and via CD is maintained. The OSG loss during etching is minimized by removing the etch stop layer at an early stage of the dual damascene sequence.
    Type: Application
    Filed: April 9, 2003
    Publication date: October 14, 2004
    Applicant: Institute of Microelectronics
    Inventors: Qiang Guo, Ahila Krishnamoorthy, Xiaomei Bu, Vladimir N. Bliznetsov
  • Publication number: 20040170221
    Abstract: A mobile wireless communications device and methods therefore, including receiving a signal (710), storing a portion of the received signal (730), identifying all possible pilot signals by determining slot boundary information for the stored signal portion (720), determining frame boundary information and/or scrambling code information (760) of the stored signal portion by correlating the stored signal portion with the scrambling codes based on the slot boundary information. In other embodiments, the search is performed in real-time without storing the signal.
    Type: Application
    Filed: February 27, 2003
    Publication date: September 2, 2004
    Inventors: Brian Storm, Qiang Guo, Ming D. Tan, Xuping Zhou, Mang Zhu