Abstract: An integration approach to improve electromigration resistance in a semiconductor device is described. A via hole is formed in a stack that includes an upper dielectric layer, a middle TiN ARC, and a lower first metal layer and is filled with a conformal diffusion barrier layer and a second metal layer. A key feature is that the etch process can be selected to vary the shape and location of the via bottom. A round or partially rounded bottom is formed in the first metal layer to reduce mechanical stress near the diffusion barrier layer. On the other hand, a flat bottom which stops on or in the TiN ARC is selected when exposure of the first metal layer to subsequent processing steps is a primary concern. Electromigration resistance is found to be lower than for a via structure with a flat bottom formed in a first metal layer.

Abstract: A mobile wireless communications device and methods therefore, including receiving a signal (710), storing a portion of the received signal (730), identifying all possible pilot signals by determining slot boundary information for the stored signal portion (720), determining frame boundary information and/or scrambling code information (760) of the stored signal portion by correlating the stored signal portion with the scrambling codes based on the slot boundary information. In other embodiments, the search is performed in real-time without storing the signal.

Abstract: An integration approach to improve electromigration resistance in a semiconductor device is described. A via hole is formed in a stack that includes an upper dielectric layer, a middle TiN ARC, and a lower first metal layer and is filled with a conformal diffusion barrier layer and a second metal layer. A key feature is that the etch process can be selected to vary the shape and location of the via bottom. A round or partially rounded bottom is formed in the first metal layer to reduce mechanical stress near the diffusion barrier layer. On the other hand, a flat bottom which stops on or in the TiN ARC is selected when exposure of the first metal layer to subsequent processing steps is a primary concern. Electromigration resistance is found to be lower than for a via structure with a flat bottom formed in a first metal layer.

Abstract: An improved method of forming a dual damascene structure that includes an organosilicate glass (OSG) dielectric layer is described. A via first process is followed in which a via is formed in the OSG layer and preferably stops on a SiC layer. The SiC layer is removed prior to stripping a photoresist containing the via pattern. A planarizing BARC layer is formed in the via to protect the exposed substrate from damage during trench formation. The method provides higher Kelvin via and via chain yields. Damage to the OSG layer at top corners of the via and trench is avoided. Furthermore, there is no pitting in the OSG layer at the trench bottom. Vertical sidewalls are achieved in the via and trench openings and via CD is maintained. The OSG loss during etching is minimized by removing the etch stop layer at an early stage of the dual damascene sequence.

Abstract: Methods and systems for recognizing a film in a scanner are provided. First, the film is previewed by the scanner to obtain an original preview image. The original preview image comprises a film image corresponding to the film. The original preview image also comprises pixels and each pixel has a first hue value, a second hue value, and a third hue value. The pixels with luminance in a predetermined range are then selected from the original preview image to acquire a second preview image. Next, the second preview image is framed according to the first hue values of the pixels to obtain an image frame. Finally, the image frame is sectioned to recognize the film image.

Abstract: An improved method of forming a dual damascene structure that includes an organosilicate glass (OSG) dielectric layer is described. A via first process is followed in which a via is formed in the OSG layer and preferably stops on a SiC layer. The SiC layer is removed prior to stripping a photoresist containing the via pattern. A planarizing BARC layer is formed in the via to protect the exposed substrate from damage during trench formation. The method provides higher Kelvin via and via chain yields. Damage to the OSG layer at top comers of the via and trench is avoided. Furthermore, there is no pitting in the OSG layer at the trench bottom. Vertical sidewalls are achieved in the via and trench openings and via CD is maintained. The OSG loss during etching is minimized by removing the etch stop layer at an early stage of the dual damascene sequence.

Abstract: A mobile wireless communications device and methods therefore, including receiving a signal (710), storing a portion of the received signal (730), identifying all possible pilot signals by determining slot boundary information for the stored signal portion (720), determining frame boundary information and/or scrambling code information (760) of the stored signal portion by correlating the stored signal portion with the scrambling codes based on the slot boundary information. In other embodiments, the search is performed in real-time without storing the signal.