Abstract: A method of programming a memory device including a cell is provided. A first program pulse is applied to the cell. Middle program pulses are applied to the cell after the application of the first program pulse. A last program pulse is applied to the cell after the application of the middle program pulses. A pulse width of the last program pulse is wider than a pulse width of each of the middle program pulses and the first program pulse.

Abstract: A method of programming a memory device including a cell is provided. A first program pulse is applied to the cell. Middle program pulses are applied to the cell after the application of the first program pulse. A last program pulse is applied to the cell after the application of the middle program pulses. A pulse width of the last program pulse is wider than a pulse width of each of the middle program pulses and the first program pulse.

Abstract: A three-dimensional (3D) memory device and a manufacturing method thereof are provided. The 3D memory device includes a substrate, insulation layers, gate material layers, and a vertical structure. The insulation layers and the gate material layers are disposed on the substrate and alternately stacked in a vertical direction. The vertical structure penetrates the gate material layers in the vertical direction. The vertical structure includes a semiconductor layer and a trapping layer. The semiconductor layer is elongated in the vertical direction. The trapping layer surrounds the semiconductor layer in a horizontal direction. The trapping layer includes trapping sections aligned in the vertical direction and separated from one another. The electrical performance of the 3D memory device may be improved by the trapping sections separated from one another.

Abstract: A memory device includes a memory array including a cell, and a controller coupled to the memory array. The controller is configured to control sequentially applying programming voltage pulses to the cell. A pulse width of each of the programming voltage pulses decreases as a pulse count of the programming voltage pulses increases.

Abstract: Aspects of the disclosure provide a method to manufacture a semiconductor device. The method includes filling a sacrificial layer in a first via of a first stack. An initial top CD is larger than an initial bottom CD of the first via. A second stack is formed along a vertical direction over the first stack. A third stack is formed along the vertical direction over the second stack. The first stack, the second stack, and the third stack include alternating insulating layers and gate layers. The insulating layers of the second stack etch at a faster rate than the insulating layers of the third stack and the gate layers of the second stack etch at a faster rate than the gate layers of the third stack. A first via, a second via, and a third via are formed in the first stack, the second stack, and the third stack, respectively.

Abstract: Embodiments of structure and methods for forming a three-dimensional (3D) memory device are provided. In an example, the memory device includes a stack structure having interleaved a plurality of conductor layers and a plurality of dielectric layers over a substrate along a vertical direction. The memory device also includes a channel structure extending in the stack structure along the vertical direction. A thickness of at least one of the plurality of dielectric layers is nominally inversely proportional to a width of the channel structure at the same depth.

Abstract: In a method for forming a semiconductor device, a channel structure is formed that extends from a side of a substrate, where the channel structure includes sidewalls and a bottom region. The channel structure further includes a bottom channel contact that is positioned at the bottom region and a channel layer that is formed along the sidewalls and over the bottom channel contact. A high-k layer is formed over the channel layer along the sidewalls of the channel structure and over the bottom channel contact.

Abstract: Embodiments of structure and methods for forming a three-dimensional (3D) memory device are provided. In an example, the memory device includes a stack structure having interleaved a plurality of conductor layers and a plurality of dielectric layers over a substrate along a vertical direction. The memory device also includes a channel structure extending in the stack structure along the vertical direction. A thickness of at least one of the plurality of conductor layers is nominally proportional to a width of the channel structure at the same depth.

Abstract: A three-dimensional (3D) memory device and a manufacturing method thereof are provided. The 3D memory device includes a substrate, insulation layers, gate material layers, and a vertical structure. The insulation layers and the gate material layers are disposed on the substrate and alternately stacked in a vertical direction. The vertical structure penetrates the gate material layers in the vertical direction. The vertical structure includes a semiconductor layer and a trapping layer. The semiconductor layer is elongated in the vertical direction. The trapping layer surrounds the semiconductor layer in a horizontal direction. The trapping layer includes trapping sections aligned in the vertical direction and separated from one another. The electrical performance of the 3D memory device may be improved by the trapping sections separated from one another.

Abstract: Aspects of the disclosure provide a semiconductor device and a method to manufacture the semiconductor device. A semiconductor device includes one or more units of strings of cells, and dielectric structures extending in a vertical direction and a first direction perpendicular to the vertical direction and separating adjacent units of strings of cells. Each unit of strings of cells includes a first string of cells each including first cells, and a second string of cells each including second cells.

Abstract: Aspects of the disclosure provide a semiconductor device including a string of transistors stacked in a vertical direction over a substrate of the semiconductor device having a channel structure extending in the vertical direction. The string of transistors includes a first substring arranged along a first portion of the channel structure, a second substring arranged along a second portion of the channel structure, and a third substring arranged along a third portion of the channel structure. The second substring is between the first and the third substrings. Gate structures of transistors in the first substring are separated by first insulating layers. Gate structures of transistors in the second substring are separated by second insulating layers. Gate structures of transistors in the third substring are separated by third insulating layers. A volumetric mass density of the second insulating layers is lower than a volumetric mass density of the third insulating layers.

Abstract: A three-dimensional (3D) memory device includes a substrate, an alternating conductive/dielectric stack disposed on the substrate, an epitaxial layer disposed on the substrate, a blocking layer disposed on the epitaxial layer and surrounded by the alternating conductive/dielectric stack, a trapping layer disposed on and surrounded by the blocking layer, a tunneling layer disposed on and surrounded by the trapping layer, and a semiconductor layer disposed on and in contact with the epitaxial layer and partially disposed on and surrounded by the tunneling layer.

Abstract: Three-dimensional (3D) NAND memory devices and methods are provided. In one aspect, a fabrication method includes forming a dielectric stack over a substrate, forming a functional layer and a semiconductor channel through the dielectric stack, forming a conductor/insulator stack based on the dielectric stack, and forming memory cells through the conductor/insulator stack. Each memory cell includes a portion of the functional layer and the semiconductor channel. At least one of the functional layer and the semiconductor channel includes a certain amount of deuterium elements.

Abstract: Three-dimensional (3D) NAND memory devices and methods are provided. In one aspect, a fabrication method includes forming a layer stack, a channel hole, a blocking layer, a charge trap layer, a tunnel insulation layer, and a channel layer. The surface region of the charge trap layer includes a carbon region that contains a certain amount of carbon elements.

Abstract: A memory device includes a stacked structure. The stacked structure includes a plurality of interlayer dielectric layers and a gate structure between adjacent interlayer dielectric layers. A charge trapping layer and a blocking layer are between the adjacent interlayer dielectric layers. The blocking layer envelops the charge trapping layer and separates the charge trapping layer from the gate structure. A tunneling layer is disposed along a sidewall of the stacked structure and in contact with each of the gate structure and the charge trapping layer. A channel layer is disposed on a sidewall of the tunneling layer.

Abstract: Embodiments of structure and methods for forming a three-dimensional (3D) memory device are provided. In an example, the memory device includes a stack structure having interleaved a plurality of sacrificial layers and a plurality of dielectric layers over a substrate along a vertical direction. The memory device also includes a channel structure extending in the stack structure along the vertical direction. A thickness of at least one of the plurality of sacrificial layers is nominally proportional to a width of the channel structure at the same depth. A thickness of at least one of the plurality of dielectric layers is nominally inversely proportional to a width of the channel structure at the same depth.

Abstract: A method for fabricating a memory device includes providing an initial semiconductor structure, including a base substrate, a stack structure of interlayer dielectric layers and first sacrificial layers; a channel trench formed through the stack structure. The method includes removing a portion of each first sacrificial layer from the channel trench to form a trapping-layer trench; forming a second sacrificial layer in the trapping-layer trench; forming a charge trapping film to fill the trapping-layer trench; and removing a portion of the charge trapping film from the channel trench to form a charge trapping layer; forming a tunneling layer and a channel layer on the sidewalls of the channel trench; removing the first sacrificial layers and the second sacrificial layer; forming a blocking layer on the charge trapping layer; and forming gate structures, in contact with the tunneling layer, between adjacent interlayer dielectric layers.

Abstract: A memory device includes a memory array including a cell, and a controller coupled to the memory array. The controller is configured to control sequentially applying programming voltage pulses to the cell. A pulse width of each of the programming voltage pulses decreases as a pulse count of the programming voltage pulses increases.

Abstract: A three-dimensional (3D) memory device and a manufacturing method thereof are provided. The 3D memory device includes a substrate, insulation layers, gate material layers, and a vertical structure. The insulation layers and the gate material layers are disposed on the substrate and alternately stacked in a vertical direction. The vertical structure penetrates the gate material layers in the vertical direction. The vertical structure includes a semiconductor layer and a trapping layer. The semiconductor layer is elongated in the vertical direction. The trapping layer surrounds the semiconductor layer in a horizontal direction. The trapping layer includes trapping sections aligned in the vertical direction and separated from one another. The electrical performance of the 3D memory device may be improved by the trapping sections separated from one another.

Abstract: A semiconductor device is provided. The semiconductor device includes a channel structure that extends from a side of a substrate. The channel structure has sidewalls and a bottom region. The channel structure includes a bottom channel contact that is positioned at the bottom region, and a channel layer that is formed along the sidewalls and over the bottom channel contact. The channel structure further includes a high-k layer that is formed over the channel layer along the sidewalls of the channel structure and over the bottom channel contact.