Patents by Inventor Qiguang Wang
Qiguang Wang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20220093641Abstract: A three-dimensional (3D) memory device and a manufacturing method thereof are provided. The 3D memory device includes a substrate, insulation layers, gate material layers, and a vertical structure. The insulation layers and the gate material layers are disposed on the substrate and alternately stacked in a vertical direction. The vertical structure penetrates the gate material layers in the vertical direction. The vertical structure includes a semiconductor layer and a trapping layer. The semiconductor layer is elongated in the vertical direction. The trapping layer surrounds the semiconductor layer in a horizontal direction. The trapping layer includes trapping sections aligned in the vertical direction and separated from one another. The electrical performance of the 3D memory device may be improved by the trapping sections separated from one another.Type: ApplicationFiled: December 1, 2021Publication date: March 24, 2022Applicant: Yangtze Memory Technologies Co., Ltd.Inventor: Qiguang Wang
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Patent number: 11282854Abstract: A semiconductor device is provided. The semiconductor device includes a channel structure that extends from a side of a substrate. The channel structure has sidewalls and a bottom region. The channel structure includes a bottom channel contact that is positioned at the bottom region, and a channel layer that is formed along the sidewalls and over the bottom channel contact. The channel structure further includes a high-k layer that is formed over the channel layer along the sidewalls of the channel structure and over the bottom channel contact.Type: GrantFiled: November 15, 2019Date of Patent: March 22, 2022Assignee: Yangtze Memory Technologies Co., Ltd.Inventors: Yingjie Ouyang, Zhiliang Xia, Lei Jin, Qiguang Wang, Wenxi Zhou, Zhongwang Sun, Rui Su, Yueqiang Pu, Jiwei Cheng
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Publication number: 20220077188Abstract: Aspects of the disclosure provide a semiconductor device and a method to manufacture the semiconductor device. A semiconductor device includes one or more units of strings of cells, and dielectric structures extending in a vertical direction and a first direction perpendicular to the vertical direction and separating adjacent units of strings of cells. Each unit of strings of cells includes a first string of cells each including first cells, and a second string of cells each including second cells.Type: ApplicationFiled: November 17, 2021Publication date: March 10, 2022Inventor: Qiguang WANG
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Patent number: 11250910Abstract: A control method of a programming process for a three-dimensional (3D) NAND flash memory array comprises programming a bit-cell of the 3D NAND flash memory array in a programming stage; and verifying whether the bit-cell of the 3D NAND flash memory array is programmed in a verification stage after the programming stage; wherein the programming stage comprises programming the bit-cell of the 3D NAND flash memory array with a plurality of programming voltage pulses; wherein the verification stage comprises reading the bit-cell of the 3D NAND flash memory array with lower or higher voltage than normal reading voltage pulse.Type: GrantFiled: June 2, 2020Date of Patent: February 15, 2022Assignee: Yangtze Memory Technologies Co., Ltd.Inventors: Ying Huang, Hongtao Liu, Qiguang Wang, Wenzhe Wei
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Publication number: 20220045098Abstract: In a method for forming a semiconductor device, a channel structure is formed that extends from a side of a substrate, where the channel structure includes sidewalls and a bottom region. The channel structure further includes a bottom channel contact that is positioned at the bottom region and a channel layer that is formed along the sidewalls and over the bottom channel contact. A high-k layer is formed over the channel layer along the sidewalls of the channel structure and over the bottom channel contact.Type: ApplicationFiled: October 22, 2021Publication date: February 10, 2022Applicant: Yangtze Memory Technologies Co., Ltd.Inventors: Yingjie OUYANG, Zhiliang XIA, Lei JIN, Qiguang WANG, Wenxi ZHOU, Zhongwang SUN, Rui SU, Yueqiang PU, Jiwei CHENG
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Patent number: 11239250Abstract: Aspects of the disclosure provide a semiconductor device and a method to manufacture the semiconductor device. A trench is formed in a stack over a substrate of the semiconductor device where the stack includes alternating first layers and second layers. The trench has a first sidewall and a second sidewall opposite to the first sidewall. Channel materials are formed along the first and second sidewalls of the trench, respectively. The trench is further divided into multiple units by replacing portions of the channel materials with first dielectric structures. Remaining portions of the channel materials along the first and second sidewalls form first and second channel structures of first and second strings of transistors, respectively. The second layers are replaced with first and second gate structures of the first and second strings of transistors, respectively. Each of the first and second strings of transistors is vertically stacked over the substrate.Type: GrantFiled: January 8, 2020Date of Patent: February 1, 2022Assignee: YANGTZE MEMORY TECHNOLOGIES CO., LTD.Inventor: Qiguang Wang
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Publication number: 20220020760Abstract: Aspects of the disclosure provide a semiconductor device including a string of transistors stacked in a vertical direction over a substrate of the semiconductor device having a channel structure extending in the vertical direction. The string of transistors includes a first substring arranged along a first portion of the channel structure, a second substring arranged along a second portion of the channel structure, and a third substring arranged along a third portion of the channel structure. The second substring is between the first and the third substrings. Gate structures of transistors in the first substring are separated by first insulating layers. Gate structures of transistors in the second substring are separated by second insulating layers. Gate structures of transistors in the third substring are separated by third insulating layers. A volumetric mass density of the second insulating layers is lower than a volumetric mass density of the third insulating layers.Type: ApplicationFiled: September 30, 2021Publication date: January 20, 2022Applicant: Yangtze Memory Technologies Co., Ltd.Inventors: Qiguang Wang, Gonglian Wu
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Publication number: 20210399000Abstract: Aspects of the disclosure provide a method to manufacture a semiconductor device. The method includes filling a sacrificial layer in a first via of a first stack. An initial top CD is larger than an initial bottom CD of the first via. A second stack is formed along a vertical direction over the first stack. A third stack is formed along the vertical direction over the second stack. The first stack, the second stack, and the third stack include alternating insulating layers and gate layers. The insulating layers of the second stack etch at a faster rate than the insulating layers of the third stack and the gate layers of the second stack etch at a faster rate than the gate layers of the third stack. A first via, a second via, and a third via are formed in the first stack, the second stack, and the third stack, respectively.Type: ApplicationFiled: August 31, 2021Publication date: December 23, 2021Applicant: Yangtze Memory Technologies Co., Ltd.Inventors: Qiguang WANG, Gonglian Wu
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Patent number: 11183508Abstract: Aspects of the disclosure provide a semiconductor device and a method to manufacture the semiconductor device. The semiconductor device includes a string of transistors stacked in a vertical direction over a substrate of the semiconductor device having a channel structure extending in the vertical direction. The string of transistors includes first, second, and third substrings of transistors that are arranged along first, second, and third portions of the channel structure, respectively. Gate structures of transistors in the first, second, and third substring are separated by respective first, second, and third insulating layers and the second insulating layers have a higher etch rate than that of the third insulating layers.Type: GrantFiled: November 20, 2019Date of Patent: November 23, 2021Assignee: Yangtze Memory Technologies Co., Ltd.Inventors: Qiguang Wang, Gonglian Wu
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Publication number: 20210358948Abstract: A three-dimensional (3D) memory device includes a substrate, an alternating conductive/dielectric stack disposed on the substrate, an epitaxial layer disposed on the substrate, a blocking layer disposed on the epitaxial layer and surrounded by the alternating conductive/dielectric stack, a trapping layer disposed on and surrounded by the blocking layer, a tunneling layer disposed on and surrounded by the trapping layer, and a semiconductor layer disposed on and in contact with the epitaxial layer and partially disposed on and surrounded by the tunneling layer.Type: ApplicationFiled: July 28, 2021Publication date: November 18, 2021Inventors: Qiguang Wang, Lei Jin, An Zhang, Jianwei Lu
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Publication number: 20210350853Abstract: A control method of a programming process for a three-dimensional (3D) NAND flash memory array comprises programming a bit-cell of the 3D NAND flash memory array in a programming stage; and verifying whether the bit-cell of the 3D NAND flash memory array is programmed in a verification stage after the programming stage; wherein the programming stage comprises programming the bit-cell of the 3D NAND flash memory array with a plurality of programming voltage pulses; wherein the verification stage comprises reading the bit-cell of the 3D NAND flash memory array with lower or higher voltage than normal reading voltage pulse.Type: ApplicationFiled: June 2, 2020Publication date: November 11, 2021Inventors: Ying Huang, Hongtao Liu, Qiguang Wang, Wenzhe Wei
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Publication number: 20210288063Abstract: A method for fabricating a memory device includes providing an initial semiconductor structure, including a base substrate, a stack structure of interlayer dielectric layers and first sacrificial layers; a channel trench formed through the stack structure. The method includes removing a portion of each first sacrificial layer from the channel trench to form a trapping-layer trench; forming a second sacrificial layer in the trapping-layer trench; forming a charge trapping film to fill the trapping-layer trench; and removing a portion of the charge trapping film from the channel trench to form a charge trapping layer; forming a tunneling layer and a channel layer on the sidewalls of the channel trench; removing the first sacrificial layers and the second sacrificial layer; forming a blocking layer on the charge trapping layer; and forming gate structures, in contact with the tunneling layer, between adjacent interlayer dielectric layers.Type: ApplicationFiled: June 18, 2020Publication date: September 16, 2021Inventors: Qiguang WANG, Jiefei FU
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Patent number: 11121152Abstract: A three-dimensional (3D) memory device and a manufacturing method thereof are provided. The method includes the following steps. An alternating dielectric stack is formed on a substrate. An opening is formed penetrating the alternating dielectric stack in a thickness direction of the substrate. A blocking layer is formed on a sidewall of the opening. A trapping layer is formed in the opening, and the trapping layer is formed on the blocking layer. The trapping layer includes a lower portion and an upper portion disposed above the lower portion. A thickness of the upper portion in a horizontal direction is greater than a thickness of the lower portion in the horizontal direction. The thickness distribution of the trapping layer is modified for improving the electrical performance of the 3D memory device.Type: GrantFiled: November 10, 2019Date of Patent: September 14, 2021Assignee: Yangtze Memory Technologies Co., Ltd.Inventors: Qiguang Wang, Lei Jin, An Zhang, Jianwei Lu
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Patent number: 11053996Abstract: A hub motor is provided with a simplified structure to make an automobile more cost effective. The hub motor includes a center shaft, a brake disc fixedly connected with the center shaft, a coil support sleeved on the center shaft, and a motor controller. The coil support advantageously includes first and second coil supports that include first and second vents, respectively.Type: GrantFiled: June 20, 2017Date of Patent: July 6, 2021Inventor: Qiguang Wang
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Publication number: 20210111185Abstract: Aspects of the disclosure provide a semiconductor device and a method to manufacture the semiconductor device. A trench is formed in a stack over a substrate of the semiconductor device where the stack includes alternating first layers and second layers. The trench has a first sidewall and a second sidewall opposite to the first sidewall. Channel materials are formed along the first and second sidewalls of the trench, respectively. The trench is further divided into multiple units by replacing portions of the channel materials with first dielectric structures. Remaining portions of the channel materials along the first and second sidewalls form first and second channel structures of first and second strings of transistors, respectively. The second layers are replaced with first and second gate structures of the first and second strings of transistors, respectively. Each of the first and second strings of transistors is vertically stacked over the substrate.Type: ApplicationFiled: January 8, 2020Publication date: April 15, 2021Applicant: YANGTZE MEMORY TECHNOLOGIES CO., LTD.Inventor: Qiguang WANG
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Publication number: 20210098487Abstract: A three-dimensional (3D) memory device and a manufacturing method thereof are provided. The method includes the following steps. An alternating dielectric stack is formed on a substrate. An opening is formed penetrating the alternating dielectric stack in a thickness direction of the substrate. A blocking layer is formed on a sidewall of the opening. A trapping layer is formed in the opening, and the trapping layer is formed on the blocking layer. The trapping layer includes a lower portion and an upper portion disposed above the lower portion. A thickness of the upper portion in a horizontal direction is greater than a thickness of the lower portion in the horizontal direction. The thickness distribution of the trapping layer is modified for improving the electrical performance of the 3D memory device.Type: ApplicationFiled: November 10, 2019Publication date: April 1, 2021Inventors: Qiguang Wang, Lei Jin, An Zhang, Jianwei Lu
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Publication number: 20210091106Abstract: A three-dimensional (3D) memory device and a manufacturing method thereof are provided. The 3D memory device includes a substrate, insulation layers, gate material layers, and a vertical structure. The insulation layers and the gate material layers are disposed on the substrate and alternately stacked in a vertical direction. The vertical structure penetrates the gate material layers in the vertical direction. The vertical structure includes a semiconductor layer and a trapping layer. The semiconductor layer is elongated in the vertical direction. The trapping layer surrounds the semiconductor layer in a horizontal direction. The trapping layer includes trapping sections aligned in the vertical direction and separated from one another. The electrical performance of the 3D memory device may be improved by the trapping sections separated from one another.Type: ApplicationFiled: October 27, 2019Publication date: March 25, 2021Inventor: Qiguang Wang
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Publication number: 20210066335Abstract: A semiconductor device is provided. The semiconductor device includes a channel structure that extends from a side of a substrate. The channel structure has sidewalls and a bottom region. The channel structure includes a bottom channel contact that is positioned at the bottom region, and a channel layer that is formed along the sidewalls and over the bottom channel contact. The channel structure further includes a high-k layer that is formed over the channel layer along the sidewalls of the channel structure and over the bottom channel contact.Type: ApplicationFiled: November 15, 2019Publication date: March 4, 2021Applicant: Yangtze Memory Technologies Co., Ltd.Inventors: Yingjie OUYANG, Zhiliang XIA, Lei JIN, Qiguang WANG, Wenxi ZHOU, Zhongwang SUN, Rui SU, Yueqiang PU, Jiwei CHENG
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Publication number: 20200411545Abstract: Embodiments of structure and methods for forming a three-dimensional (3D) memory device are provided. In an example, the memory device includes a stack structure having interleaved a plurality of sacrificial layers and a plurality of dielectric layers over a substrate along a vertical direction. The memory device also includes a channel structure extending in the stack structure along the vertical direction. A thickness of at least one of the plurality of sacrificial layers is nominally proportional to a width of the channel structure at the same depth. A thickness of at least one of the plurality of dielectric layers is nominally inversely proportional to a width of the channel structure at the same depth.Type: ApplicationFiled: April 30, 2020Publication date: December 31, 2020Inventors: Qiguang Wang, Wenxi Zhou
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Publication number: 20200411535Abstract: Aspects of the disclosure provide a semiconductor device and a method to manufacture the semiconductor device. The semiconductor device includes a string of transistors stacked in a vertical direction over a substrate of the semiconductor device having a channel structure extending in the vertical direction. The string of transistors includes first, second, and third substrings of transistors that are arranged along first, second, and third portions of the channel structure, respectively. Gate structures of transistors in the first, second, and third substring are separated by respective first, second, and third insulating layers and the second insulating layers have a higher etch rate than that of the third insulating layers.Type: ApplicationFiled: November 20, 2019Publication date: December 31, 2020Applicant: Yangtze Memory Technologies Co., Ltd.Inventors: Qiguang WANG, Gonglian Wu