Abstract: A method for green synthesis of uniform- and large-particle-size polystyrene particles, comprising steps of: prepolymerizing styrene at 70? to 75? for 1 h to 6 h in advance while stirring, adding divinylbenzene dissolved with initiators to the styrene, and stirring for 10 min to 30 min to obtain oil phase; heating lactic acid or an aqueous solution of lactic acid to 70? to 80?, adding the oil phase to dispersed phase by a constant-pressure device, maintaining the temperature for 2 h, heating to 80±5? and then maintaining the temperature for 1 h, and heating to 85±5? and then maintaining the temperature for 3 h to 6 h, to obtain polystyrene particles with a uniform particle size ranging from 0.7 mm to 2.0 mm.

Abstract: The present invention relates to a blower vacuum device having a housing with an air inlet and an air outlet, a motor accommodated in the housing, a fan driven by the motor, and a plurality of blowing accessories adapted to be connected to the air outlet respectively when the suction or blower device works. These different blowing accessories can perform various cleaning functions, thus meeting the cleaning demands in different places or in a specific area.

Abstract: According to at least some embodiments of the present disclosure, a light-emitting diode (LED) chip includes a semiconductor material portion, a transparent conductive layer disposed above the semiconductor material portion, a current blocking layer disposed above the transparent conductive layer, one or more electrodes disposed above the current blocking layer, and a plurality of electron outflow channels that electrically interconnect at least one electrode and the semiconductor material portion across the transparent conductive layer and the current blocking layer.

Abstract: A packet generation method based on a server cluster and a load balancer, where the method includes receiving a client request packet, determining a destination server according to a preset load balancing policy, sending an Address Resolution Protocol (ARP) request packet according to the destination Internet Protocol (IP) address, obtaining an ARP response packet according to the ARP request packet, the initial Media Access Control (MAC) address is different from an actual MAC address of the destination server, and updating the destination IP address according to the initial MAC address to obtain an updated client request packet, where the updated client request packet includes the source IP address and an updated destination IP address. In this way, in a process of transmitting a packet, a source IP address of a client is detected on a network layer without changing a source IP address in a request packet.

Abstract: According to at least some embodiments of the present disclosure, a light-emitting diode (LED) chip includes a semiconductor material portion, a transparent conductive layer disposed above the semiconductor material portion, a current blocking layer disposed above the transparent conductive layer, one or more electrodes disposed above the current blocking layer, and a plurality of electron outflow channels that electrically interconnect at least one electrode and the semiconductor material portion across the transparent conductive layer and the current blocking layer.

Abstract: Passivation of group III-nitride hetero junction devices is described herein. The passivation facilitates simultaneous realization of effective/high current collapse suppression and low leakage current without the use of a sophisticated multiple-field plate technique. The passivation can be achieved by growing a charge-polarized AlN thin film on the surface of a group III-nitride based heterojunction device by plasma-enhanced atomic layer deposition such that positive polarization charges are induced at the interface to compensate for a majority of negative charges at the interface.

Abstract: Passivation of group III-nitride hetero junction devices is described herein. The passivation facilitates simultaneous realization of effective/high current collapse suppression and low leakage current without the use of a sophisticated multiple-field plate technique. The passivation can be achieved by growing a charge-polarized. AlN thin film on the surface of a group III-nitride based heterojunction device by plasma-enhanced atomic layer deposition such that positive polarization charges are induced at the interface to compensate for a majority of negative charges at the interface.

Abstract: Passivation of group III-nitride heterojunction devices is described herein. The passivation facilitates simultaneous realization of effective/high current collapse suppression and low leakage current without the use of a sophisticated multiple-field plate technique. The passivation can be achieved by growing a charge-polarized AlN thin film on the surface of a group III-nitride based heterojunction device by plasma-enhanced atomic layer deposition such that positive polarization charges are induced at the interface to compensate for a majority of negative charges at the interface.

Abstract: The present invention relates to a suction or blower device, comprising a housing having an air inlet and an air outlet, a motor accommodated in the housing, a fan driven by the motor, and a plurality of blowing accessories adapted to be connected to the air outlet respectively when the suction or blower device works. These different blowing accessories can perform various cleaning functions, thus meeting the cleaning demands in different places or in a specific area.

Abstract: Passivation of group III-nitride heterojunction devices is described herein. The passivation facilitates simultaneous realization of effective/high current collapse suppression and low leakage current without the use of a sophisticated multiple-field plate technique. The passivation can be achieved by growing a charge-polarized AlN thin film on the surface of a group III-nitride based heterojunction device by plasma-enhanced atomic layer deposition such that positive polarization charges are induced at the interface to compensate for a majority of negative charges at the interface.

Abstract: A customer profiling apparatus is provided for conducting customer behavior pattern analysis. The apparatus includes processing circuitry, a data warehouse, a profiling engine, and at least one computer program. The processing circuitry is operative to process customer records. The data warehouse is coupled with the processing circuitry and is configured to store the processed customer records. The profiling engine communicates with the data warehouse and is operative to build and update customer behavior profiles by mining the customer records that flow into the data warehouse. The at least one computer program is performed by the profiling engine, and is operative to define behavior profiles as data cubes and derive similarity measures on patterns extracted from the behavior profiles. A method is also provided.

Abstract: A reference voltage circuit is disclosed that is independent of the voltage supply as well as substantially insensitive to process and temperature variations. The reference voltage circuit includes an intrinsic transistor circuit which includes a plurality of intrinsic transistors of equal size. The intrinsic transistor circuit is coupled to a current mirror circuit, and a plurality of threshold transistors. In so doing, a reference voltage circuit is provided that is substantially independent of process and temperature variations. In addition, by grounding the source connections of the plurality of threshold transistors, the reference voltage circuit output voltage also is substantially independent of supply voltage variations.

Abstract: A method for programming multiple values in an individual flash memory cell is disclosed. An individual flash cell is programmed by holding the bit line, corresponding to the particular memory cell to a value, V.sub.d, while the voltage on the control gate, V.sub.g, of the memory cell is varied. By varying the voltage on the control gate, multiple values are stored in the memory cell. The resulting values are self-convergent, therefore, verify circuitry becomes unnecessary.

Abstract: A flash memory device having a reduced area is disclosed. The device uses a polyI layer to act as a select transistor for the memory cells comprising the core array. Also, a ground plate is used to isolate the areas of the memory array where high voltage devices should not be located, thereby allowing peripheral components to be fabricated in the core array area. Also disclosed is a polyII layer used to access two sublines controlling two different sectors of the memory array architecture. By using such a layout, die space savings is attained.

Abstract: An improved reading structure (110) for performing a read operation in an array of multiple bits-per-cell flash EEPROM memory cells is provided. A memory core array (12) includes a plurality of memory cells, each being previously programmed to one of a plurality of memory conditions defined by memory core threshold voltages. A reference cell array (22) includes a plurality of reference core cells which are selected together with a selected core cell and provides selectively one of a plurality of reference cell bit line voltages defined by reference cell threshold voltages. Each of the reference cells are previously programmed at the same time as when the memory core cells are being programmed. A precharge circuit (36) is used to precharge the array bit lines and the reference bit lines to a predetermined potential. A detector circuit (28) is responsive to the bit line voltages of the reference cells for generating strobe signals.

Abstract: A shift register page buffer for use in an array of multiple bits-per-cell flash EEPROM memory cells so as to render page mode programming and reading is provided. A sensing logic circuit (26,27) is used to selectively and sequentially compare array bit line voltages with each of a plurality of target reference cell bit line voltages. Shift register circuit (300) is responsive to the sensing logic circuit for sequentially storing either a low or high logic level after each comparison of the bit line voltages with one of the plurality of target reference voltages. Each of the shift register circuits is formed of series-connected latch circuits (302-308), each having inputs and outputs. A switching transistor (N5) is interconnected between the sensing logic circuit and the latch circuits and is responsive to a corresponding output of the latch circuits for selectively passing the logic signal from the sensing circuit means to the input of the latch circuits.