Patents by Inventor Qin-Yi Tong

Qin-Yi Tong has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20120097638
    Abstract: A method for bonding at low or room temperature includes steps of surface cleaning and activation by cleaning or etching. The method may also include removing by-products of interface polymerization to prevent a reverse polymerization reaction to allow room temperature chemical bonding of materials such as silicon, silicon nitride and SiO2. The surfaces to be bonded are polished to a high degree of smoothness and planarity. VSE may use reactive ion etching or wet etching to slightly etch the surfaces being bonded. The surface roughness and planarity are not degraded and may be enhanced by the VSE process. The etched surfaces may be rinsed in solutions such as ammonium hydroxide or ammonium fluoride to promote the formation of desired bonding species on the surfaces.
    Type: Application
    Filed: December 30, 2011
    Publication date: April 26, 2012
    Applicant: Ziptronix, Inc.
    Inventors: Qin-Yi TONG, Gaius Gillman FOUNTAIN, JR., Paul M. ENQUIST
  • Patent number: 8163373
    Abstract: A method of bonding includes using a bonding layer having a fluorinated oxide. Fluorine may be introduced into the bonding layer by exposure to a fluorine-containing solution, vapor or gas or by implantation. The bonding layer may also be formed using a method where fluorine is introduced into the layer during its formation. The surface of the bonding layer is terminated with a desired species, preferably an NH2 species. This may be accomplished by exposing the bonding layer to an NH4OH solution. High bonding strength is obtained at room temperature. The method may also include bonding two bonding layers together and creating a fluorine distribution having a peak in the vicinity of the interface between the bonding layers. One of the bonding layers may include two oxide layers formed on each other. The fluorine concentration may also have a second peak at the interface between the two oxide layers.
    Type: Grant
    Filed: November 26, 2010
    Date of Patent: April 24, 2012
    Assignee: Ziptronix, Inc.
    Inventor: Qin-Yi Tong
  • Patent number: 8153505
    Abstract: A method for bonding at low or room temperature includes steps of surface cleaning and activation by cleaning or etching. The method may also include removing by-products of interface polymerization to prevent a reverse polymerization reaction to allow room temperature chemical bonding of materials such as silicon, silicon nitride and SiO2. The surfaces to be bonded are polished to a high degree of smoothness and planarity. VSE may use reactive ion etching or wet etching to slightly etch the surfaces being bonded. The surface roughness and planarity are not degraded and may be enhanced by the VSE process. The etched surfaces may be rinsed in solutions such as ammonium hydroxide or ammonium fluoride to promote the formation of desired bonding species on the surfaces.
    Type: Grant
    Filed: November 26, 2010
    Date of Patent: April 10, 2012
    Assignee: Ziptronix, Inc.
    Inventors: Qin-Yi Tong, Gaius Gillman Fountain, Jr., Paul M. Enquist
  • Patent number: 8053329
    Abstract: A method for bonding at low or room temperature includes steps of surface cleaning and activation by cleaning or etching. The method may also include removing by-products of interface polymerization to prevent a reverse polymerization reaction to allow room temperature chemical bonding of materials such as silicon, silicon nitride and SiO2. The surfaces to be bonded are polished to a high degree of smoothness and planarity. VSE may use reactive ion etching or wet etching to slightly etch the surfaces being bonded. The surface roughness and planarity are not degraded and may be enhanced by the VSE process. The etched surfaces may be rinsed in solutions such as ammonium hydroxide or ammonium fluoride to promote the formation of desired bonding species on the surfaces.
    Type: Grant
    Filed: June 29, 2009
    Date of Patent: November 8, 2011
    Assignee: Ziptronix, Inc.
    Inventors: Qin-Yi Tong, Gaius Gillman Fountain, Jr., Paul M. Enquist
  • Publication number: 20110143150
    Abstract: A method of bonding includes using a bonding layer having a fluorinated oxide. Fluorine may be introduced into the bonding layer by exposure to a fluorine-containing solution, vapor or gas or by implantation. The bonding layer may also be formed using a method where fluorine is introduced into the layer during its formation. The surface of the bonding layer is terminated with a desired species, preferably an NH2 species. This may be accomplished by exposing the bonding layer to an NH4OH solution. High bonding strength is obtained at room temperature. The method may also include bonding two bonding layers together and creating a fluorine distribution having a peak in the vicinity of the interface between the bonding layers. One of the bonding layers may include two oxide layers formed on each other. The fluorine concentration may also have a second peak at the interface between the two oxide layers.
    Type: Application
    Filed: November 26, 2010
    Publication date: June 16, 2011
    Applicant: Ziptronix, Inc.
    Inventor: Qin-Yi TONG
  • Publication number: 20110067803
    Abstract: A method for bonding at low or room temperature includes steps of surface cleaning and activation by cleaning or etching. The method may also include removing by-products of interface polymerization to prevent a reverse polymerization reaction to allow room temperature chemical bonding of materials such as silicon, silicon nitride and SiO2. The surfaces to be bonded are polished to a high degree of smoothness and planarity. VSE may use reactive ion etching or wet etching to slightly etch the surfaces being bonded. The surface roughness and planarity are not degraded and may be enhanced by the VSE process. The etched surfaces may be rinsed in solutions such as ammonium hydroxide or ammonium fluoride to promote the formation of desired bonding species on the surfaces.
    Type: Application
    Filed: November 26, 2010
    Publication date: March 24, 2011
    Applicant: Ziptronix, Inc.
    Inventors: Qin-Yi Tong, Gaius Gillman Fountain, JR., Paul M. Enquist
  • Publication number: 20110041329
    Abstract: A bonded device structure including a first substrate having a first set of metallic bonding pads, preferably connected to a device or circuit, and having a first non-metallic region adjacent to the metallic bonding pads on the first substrate, a second substrate having a second set of metallic bonding pads aligned with the first set of metallic bonding pads, preferably connected to a device or circuit, and having a second non-metallic region adjacent to the metallic bonding pads on the second substrate, and a contact-bonded interface between the first and second set of metallic bonding pads formed by contact bonding of the first non-metallic region to the second non-metallic region. At least one of the first and second substrates may be elastically deformed.
    Type: Application
    Filed: October 27, 2010
    Publication date: February 24, 2011
    Applicant: Ziptronix, Inc.
    Inventors: Qin-Yi Tong, Paul M. Enquist, Anthony Scot Rose
  • Patent number: 7871898
    Abstract: A method for bonding at low or room temperature includes steps of surface cleaning and activation by cleaning or etching. The method may also include removing by-products of interface polymerization to prevent a reverse polymerization reaction to allow room temperature chemical bonding of materials such as silicon, silicon nitride and SiO2. The surfaces to be bonded are polished to a high degree of smoothness and planarity. VSE may use reactive ion etching or wet etching to slightly etch the surfaces being bonded. The surface roughness and planarity are not degraded and may be enhanced by the VSE process. The etched surfaces may be rinsed in solutions such as ammonium hydroxide or ammonium fluoride to promote the formation of desired bonding species on the surfaces.
    Type: Grant
    Filed: March 9, 2010
    Date of Patent: January 18, 2011
    Assignee: Ziptronix, Inc.
    Inventors: Qin-Yi Tong, Gaius Gillman Fountain, Jr., Paul M. Enquist
  • Patent number: 7862885
    Abstract: A method of bonding includes using a bonding layer having a fluorinated oxide. Fluorine may be introduced into the bonding layer by exposure to a fluorine-containing solution, vapor or gas or by implantation. The bonding layer may also be formed using a method where fluorine is introduced into the layer during its formation. The surface of the bonding layer is terminated with a desired species, preferably an NH2 species. This may be accomplished by exposing the bonding layer to an NH4OH solution. High bonding strength is obtained at room temperature. The method may also include bonding two bonding layers together and creating a fluorine distribution having a peak in the vicinity of the interface between the bonding layers. One of the bonding layers may include two oxide layers formed on each other. The fluorine concentration may also have a second peak at the interface between the two oxide layers.
    Type: Grant
    Filed: December 17, 2007
    Date of Patent: January 4, 2011
    Assignee: Ziptronix, Inc.
    Inventor: Qin-Yi Tong
  • Patent number: 7842540
    Abstract: A bonded device structure including a first substrate having a first set of metallic bonding pads, preferably connected to a device or circuit, and having a first non-metallic region adjacent to the metallic bonding pads on the first substrate, a second substrate having a second set of metallic bonding pads aligned with the first set of metallic bonding pads, preferably connected to a device or circuit, and having a second non-metallic region adjacent to the metallic bonding pads on the second substrate, and a contact-bonded interface between the first and second set of metallic bonding pads formed by contact bonding of the first non-metallic region to the second non-metallic region. At least one of the first and second substrates may be elastically deformed.
    Type: Grant
    Filed: June 5, 2007
    Date of Patent: November 30, 2010
    Assignee: Ziptronix, Inc.
    Inventors: Qin-Yi Tong, Paul M. Enquist, Anthony Scot Rose
  • Patent number: 7807549
    Abstract: A method for bonding at low or room temperature includes steps of surface cleaning and activation by cleaning or etching. One etching process The method may also include removing by-products of interface polymerization to prevent a reverse polymerization reaction to allow room temperature chemical bonding of materials such as silicon, silicon nitride and SiO2. The surfaces to be bonded are polished to a high degree of smoothness and planarity. VSE may use reactive ion etching or wet etching to slightly etch the surfaces being bonded. The surface roughness and planarity are not degraded and may be enhanced by the VSE process. The etched surfaces may be rinsed in solutions such as ammonium hydroxide or ammonium fluoride to promote the formation of desired bonding species on the surfaces.
    Type: Grant
    Filed: October 31, 2007
    Date of Patent: October 5, 2010
    Assignee: Ziptronix, Inc.
    Inventors: Qin-Yi Tong, Gaius Gillman Fountain, Jr., Paul M. Enquist
  • Patent number: 7781307
    Abstract: A method for bonding at low or room temperature includes steps of surface cleaning and activation by cleaning or etching. The method may also include removing by-products of interface polymerization to prevent a reverse polymerization reaction to allow room temperature chemical bonding of materials such as silicon, silicon nitride and SiO2. The surfaces to be bonded are polished to a high degree of smoothness and planarity. VSE may use reactive ion etching or wet etching to slightly etch the surfaces being bonded. The surface roughness and planarity are not degraded and may be enhanced by the VSE process. The etched surfaces may be rinsed in solutions such as ammonium hydroxide or ammonium fluoride to promote the formation of desired bonding species on the surfaces.
    Type: Grant
    Filed: June 29, 2009
    Date of Patent: August 24, 2010
    Assignee: Ziptronix, Inc.
    Inventors: Qin-Yi Tong, Gaius Gillman Fountain, Jr., Paul M. Enquist
  • Publication number: 20100163169
    Abstract: A method for bonding at low or room temperature includes steps of surface cleaning and activation by cleaning or etching. The method may also include removing by-products of interface polymerization to prevent a reverse polymerization reaction to allow room temperature chemical bonding of materials such as silicon, silicon nitride and SiO2. The surfaces to be bonded are polished to a high degree of smoothness and planarity. VSE may use reactive ion etching or wet etching to slightly etch the surfaces being bonded. The surface roughness and planarity are not degraded and may be enhanced by the VSE process. The etched surfaces may be rinsed in solutions such as ammonium hydroxide or ammonium fluoride to promote the formation of desired bonding species on the surfaces.
    Type: Application
    Filed: March 9, 2010
    Publication date: July 1, 2010
    Applicant: Ziptronix, Inc.
    Inventors: Qin-Yi TONG, Gaius Gillman FOUNTAIN, JR., Paul M. ENQUIST
  • Patent number: 7622324
    Abstract: A method for providing encapsulation of an electronic device which obtains an encapsulating member configured to enclose the electronic device, prepares a surface of the encapsulating member for non-adhesive direct bonding, prepares a surface of a device carrier including the electronic device for non-adhesive direct bonding, and bonds the prepared surface of the encapsulating member to the prepared surface of the device carrier to form an encapsulation of the electronic device. As such, an encapsulated electronic device results which includes the device carrier having a first bonding region encompassing the electronic device, includes the encapsulating member having at least one relief preventing contact between the electronic device and the encapsulating member and having a second bonding region bonded to the first bonding region of the device carrier, and includes a non-adhesive direct bond formed between the first and second bonding regions thereby to form an encapsulation of the electronic device.
    Type: Grant
    Filed: August 9, 2004
    Date of Patent: November 24, 2009
    Assignee: Ziptronix
    Inventors: Paul M. Enquist, Qin-Yi Tong, Gaius Gillman Fountain, Jr., Robert Markunas
  • Publication number: 20090263953
    Abstract: A method for bonding at low or room temperature includes steps of surface cleaning and activation by cleaning or etching. The method may also include removing by-products of interface polymerization to prevent a reverse polymerization reaction to allow room temperature chemical bonding of materials such as silicon, silicon nitride and SiO2. The surfaces to be bonded are polished to a high degree of smoothness and planarity. VSE may use reactive ion etching or wet etching to slightly etch the surfaces being bonded. The surface roughness and planarity are not degraded and may be enhanced by the VSE process. The etched surfaces may be rinsed in solutions such as ammonium hydroxide or ammonium fluoride to promote the formation of desired bonding species on the surfaces.
    Type: Application
    Filed: June 29, 2009
    Publication date: October 22, 2009
    Applicant: Ziptronix, Inc.
    Inventors: Qin-Yi Tong, Gaius Gillman Fountain, JR., Paul M. Enquist
  • Patent number: 7602070
    Abstract: A bonded device structure including a first substrate having a first set of metallic bonding pads, preferably connected to a device or circuit, and having a first non-metallic region adjacent to the metallic bonding pads on the first substrate, a second substrate having a second set of metallic bonding pads aligned with the first set of metallic bonding pads, preferably connected to a device or circuit, and having a second non-metallic region adjacent to the metallic bonding pads on the second substrate, and a contact-bonded interface between the first and second set of metallic bonding pads formed by contact bonding of the first non-metallic region to the second non-metallic region. At least one of the first and second substrates may be elastically deformed.
    Type: Grant
    Filed: March 22, 2005
    Date of Patent: October 13, 2009
    Assignee: Ziptronix, Inc.
    Inventors: Qin-Yi Tong, Paul M. Enquist, Anthony Scot Rose
  • Patent number: 7553744
    Abstract: A method for bonding at low or room temperature includes steps of surface cleaning and activation by cleaning or etching. One etching process The method may also include removing by-products of interface polymerization to prevent a reverse polymerization reaction to allow room temperature chemical bonding of materials such as silicon, silicon nitride and SiO2. The surfaces to be bonded are polished to a high degree of smoothness and planarity. VSE may use reactive ion etching or wet etching to slightly etch the surfaces being bonded. The surface roughness and planarity are not degraded and may be enhanced by the VSE process. The etched surfaces may be rinsed in solutions such as ammonium hydroxide or ammonium fluoride to promote the formation of desired bonding species on the surfaces.
    Type: Grant
    Filed: October 31, 2007
    Date of Patent: June 30, 2009
    Assignee: Ziptronix, Inc.
    Inventors: Qin-Yi Tong, Gaius Gillman Fountain, Jr., Paul M. Enquist
  • Publication number: 20090068831
    Abstract: A method of three-dimensionally integrating elements such as singulated die or wafers and an integrated structure having connected elements such as singulated dies or wafers. Either or both of the die and wafer may have semiconductor devices formed therein. A first element having a first contact structure is bonded to a second element having a second contact structure. First and second contact structures can be exposed at bonding and electrically interconnected as a result of the bonding. A via may be etched and filled after bonding to expose and form an electrical interconnect to interconnected first and second contact structures and provide electrical access to this interconnect from a surface. Alternatively, first and/or second contact structures are not exposed at bonding, and a via is etched and filled after bonding to electrically interconnect first and second contact structures and provide electrical access to interconnected first and second contact structure to a surface.
    Type: Application
    Filed: November 13, 2008
    Publication date: March 12, 2009
    Applicant: Ziptronix
    Inventors: Paul M. Enquist, Gaius Gillman Fountain, JR., Qin-Yi Tong
  • Patent number: 7485968
    Abstract: A method of three-dimensionally integrating elements such as singulated die or wafers and an integrated structure having connected elements such as singulated dies or wafers. Either or both of the die and wafer may have semiconductor devices formed therein. A first element having a first contact structure is bonded to a second element having a second contact structure. First and second contact structures can be exposed at bonding and electrically interconnected as a result of the bonding. A via may be etched and filled after bonding to expose and form an electrical interconnect to interconnected first and second contact structures and provide electrical access to this interconnect from a surface. Alternatively, first and/or second contact structures are not exposed at bonding, and a via is etched and filled after bonding to electrically interconnect first and second contact structures and provide electrical access to interconnected first and second contact structure to a surface.
    Type: Grant
    Filed: August 11, 2005
    Date of Patent: February 3, 2009
    Assignee: Ziptronix, Inc.
    Inventors: Paul M. Enquist, Gaius Gillman Fountain, Jr., Qin-Yi Tong
  • Patent number: 7462552
    Abstract: A method for detachable bonding that forms an amorphous silicon layer, or a silicon oxide layer with a high hydrogen content, on an element such as a carrier substrate. A second element, such as a substrate, is bonded to the amorphous silicon layer or silicon oxide layer, and the second element may then have a portion removed. A third element, such as a host or carrier substrate, is bonded to the second element or to the remaining portion of the second element to form a bonded structure. The bonded structure is then heated to cause the first element to detach from the bonded structure.
    Type: Grant
    Filed: May 23, 2005
    Date of Patent: December 9, 2008
    Assignee: Ziptronix, Inc.
    Inventors: Qin-Yi Tong, Gaius Gillman Fountain, Jr.