Abstract: An electrical connector includes a base seat, a plurality of contacts fixed in the base seat, and a shielding shell surrounding the base seat. The shielding shell defines a body portion retained in the base seat, a rear wall attached a rear face of the base seat and a plurality of soldering portions extending outside of the body portion. The electrical connector defines a mounting surface, a lower edge of the rear wall is higher than the mounting surface and defines at least one board-lock portion to improve the resonant frequency.

Abstract: An electrical connector includes a first terminal module, a second terminal module, a shielding shell and a metallic shielding plate. The first terminal module includes a first mating tongue and first terminals insert molded thereamong. The first mating tongue has a first mating face on which the first terminals are exposed. The first terminals have first connecting sections extending in a vertical direction. The second terminal module includes a second mating tongue and second terminals insert molded thereamong. The second mating tongue has a second mating face directly facing to the first mating face and a third mating face. The second terminals are disposed in the second and third mating faces and have second connecting sections extending in the vertical direction. The metallic shielding plate is disposed between the first and second connecting sections and has a plurality of hooked shrapnels elastically contacting with the shielding shell.

Abstract: A method and device for a compact microstrip bandpass filter that includes an input terminal, an output terminal, a plurality of quarter-wavelength resonators, a resonant disk, a plurality of layers, and a microstrip line which connects the resonant disk to a joint point of the quarter-wavelength resonators. A method of forming two signal paths in a compact microstrip bandpass filter includes forming a first signal path between an input terminal and an output terminal of the filter with a plurality of quarter-wavelength resonators with a resonant disk and a microstrip line which connects the resonant disk to a joint point of the quarter-wavelength resonators. The method includes forming a second signal path of the quarter-wavelength resonators, the filter includes a plurality of layers.

Abstract: An electrical connector comprises an insulative housing, a plurality of contacts retained in the insulative housing and including a grounding contact and a first pair of differential signal contacts. The first pair of differential signal contacts have a first signal contact and a second signal contact closing to the grounding contact. Each contact has a contacting portion, a soldering portion, a position portion and a connecting portion. A first distance is defined between a center line of the grounding contact and an inner side edge of the connecting portion of the second signal contact, a second distance is defined between the center line and an inner side edge of the soldering portion, and a third distance is defined between the center line and the position portion, the second distance and the third distance are both smaller than the first distance.

Abstract: An electrical connector comprises an insulative housing, a plurality of contacts retained in the insulative housing and including a grounding contact and a first pair of differential signal contacts. The first pair of differential signal contacts have a first signal contact and a second signal contact closing to the grounding contact. Each contact has a contacting portion, a soldering portion, a position portion and a connecting portion. A first distance is defined between a center line of the grounding contact and an inner side edge of the connecting portion of the second signal contact, a second distance is defined between the center line and an inner side edge of the soldering portion, and a third distance is defined between the center line and the position portion, the second distance and the third distance are both smaller than the first distance.

Abstract: An electrical connector includes a base seat, a plurality of contacts fixed in the base seat, and a shielding shell surrounding the base seat. The shielding shell defines a body portion retained in the base seat, a rear wall attached a rear face of the base seat and a plurality of soldering portions extending outside of the body portion. The electrical connector defines a mounting surface, a lower edge of the rear wall is higher than the mounting surface and defines at least one board-lock portion to improve the resonant frequency.

Abstract: The present invention discloses a data management method, device and data chip. The data management method includes: receiving write data of a write request; writing the write data according to a current data management mode, where when the data management mode is a first mode, the write data of the write request is stored in an on-chip cache and when the data management mode is a second mode, the write data of the write request is stored in the on-chip cache and an off-chip memory chip; and receiving a read request of the write data, searching for the write data in the on-chip cache according to the read request, and if the write data cannot be obtained from the on-chip cache, obtaining the write data from the off-chip memory chip, thereby reducing power consumption for data access to external memory chips.

Abstract: A system and a method for writing cache data and a system and a method for reading cache data are disclosed. The system for writing the cache data includes: an on-chip memory device, configured to cache received write requests and write data associated with the write requests and sort the write requests; a request judging device, configured to extract the sorted write requests and the write data associated with the write requests according to write time sequence restriction information of an off-chip memory device; and an off-chip memory device controller, configured to write the write data extracted by the request judging device in the off-chip memory device.

Abstract: A method for making a housing comprises providing a transparent film; forming a metallic coating on the film; forming a protective coating on the metallic coating; and molding a substrate on the protective coating. A housing made by the method is also described there.

Abstract: A system and a method for writing cache data and a system and a method for reading cache data are disclosed. The system for writing the cache data includes: an on-chip memory device, configured to cache received write requests and write data associated with the write requests and sort the write requests; a request judging device, configured to extract the sorted write requests and the write data associated with the write requests according to write time sequence restriction information of an off-chip memory device; and an off-chip memory device controller, configured to write the write data extracted by the request judging device in the off-chip memory device. With a combination of the on-chip and off-chip memory devices, a large-capacity data storage space and a high-speed read and write efficiency is achieved.

Abstract: A plastic housing comprises a transparent exterior coating, a metallic coating and a substrate. The exterior coating has a first surface and a second surface. A partial of the first surface of the exterior coating is defined a plurality of groove groups thereon. The metallic coating is formed on the second surface of the exterior coating. The substrate is bonded with the metallic coating. A method for making the plastic housing is also described there.

Abstract: A method, an apparatus, and a system for processing buffered data are disclosed. The method includes: packing data packets in a same queue; splitting the packed data packet into multiple data cells according to a predetermined cell size; and storing the split data cells in multiple memories. The preceding method, apparatus, and system improve the read and write efficiency of the memories and improve the balance of the read and write bandwidths among multiple memories, thus improving the system performance.

Abstract: A housing comprises a base and a decorative film. The decorative film comprises a transparent substrate and a non-conductive coating. The substrate includes a substrate outer surface opposite to a substrate inner surface. The non-conductive coating is laminated with the substrate covering the substrate inner surface. The base is integrally molded with the decorative film covering the non-conductive coating.

Abstract: A housing, comprising: a substrate; and a vacuum depositing coating formed on the substrate by vacuum depositing method, the vacuum depositing coating including a first metal coating, a second metal coating formed on the first metal coating, and a third metal coating formed on the second metal coating; wherein the first metal coating is an aluminum coating having a light transmittance of about 25-35%, the second metal coating is a silicon dioxide coating having a thickness of about 150-450 nm, and the third metal coating is a titanium coating having a light transmittance of about 45-55%. A method for making the housing is also described.

Abstract: A device housing, comprising: a plastic substrate; a base paint layer formed on one surface of the substrate; a vacuum coated layer formed on the base paint layer, the vacuum coated layer having a metallic appearance; a transparent middle paint layer formed on the vacuum coated layer; a pattern layer formed on parts of the middle paint layer, the pattern layer having a predetermined pattern; and a transparent top paint layer formed on the surface of the pattern layer and the parts of the middle paint layer not covered by the pattern layer, the top paint layer being made of a paint having a soft tactility. A method for making the present device housing is provided.

Abstract: A device housing includes a substrate made of plastic, a base paint layer formed on the substrate surface, a vacuum coated layer formed on the base paint layer, a portion of the vacuum coated layer being textured out to form a pattern thereon, a transparent middle paint layer formed on the vacuum coated layer, and a transparent top layer formed on the middle paint layer, the top layer made of paint a having a soft tactility.

Abstract: According to one embodiment, the invention is directed to a facility for providing Asynchronous Transfer Mode (ATM) and Internet Protocol (IP) Quality of Service (QoS) features in a digital communication node. The facility includes a plurality of logical input ports, a plurality of logical output ports, ATM switching elements, IP routing elements and QoS elements. The switching and forwarding elements transfer ATM data cells and IP data packets from the logical input ports to the logical output ports. The QoS elements prioritize, schedule and flow control the transfer of data, based at least in part on ATM QoS features associated with the ATM data cells and on IP QoS features associated with the IP data packets.

Abstract: In an ATM network, a traffic management system is provided to allow simple nd effective implementation of rate-based available bit rate, or ABR, flow control at ATM switches, with the subject system using an innovative queue length based approach to calculate the cell rate that a source system can use to send cells. In one embodiment, the cell rate is calculated as an exponential function of the cell queue length at a switch, and the rate value is carried back to a source system via resource management, or RM, cells. The exponential rate calculation function provides a large stability region for a network for better flow control performance than other systems, with the subject system being easy to implement in ATM switches.

Abstract: In a cell switched network such as an ATM network, a connection admission ntrol system is provided to establish connections which guarantee user requested end-to-end cell transmission delay bounds. The subject system uses, a bit stream approach to model the worst case cell generation pattern of a connection and provides mechanisms to construct new bit streams after the original ones are delayed, multiplexed, demultiplexed, or filtered within a network. Given arriving bit streams at a queueing point, a system is provided to obtain the worst-case cell queueing delay which is used to check if a connection can be established with the requested delay bounds. In one embodiment, the subject system uses the CBR/VBR traffic models as defined in the ATM Forum Traffic Management Specification Version 4.0 to derive the worst-case bit stream for a connection and calculates the worst case queueing delay based on the conventional static priority First In First Out, or FIFO, cell transmission scheduling at switches.