Abstract: A complementary storage unit and a method of preparing the same, and a complementary memory. The complementary storage unit includes: a control transistor, a pull-up diode and a pull-down diode. The control transistor is configured to control reading and writing of the storage unit. One end of the pull-up diode is connected to a positive selection line, and the other end thereof is connected to a source end of the control transistor, so as to control a high-level input. One end of the pull-down diode is connected to a negative selection line, and the other end thereof is connected to the source end of the control transistor, so as to control a low-level input. The pull-up diode and the pull-down diode are symmetrically arranged in a first direction.

Abstract: A driving circuit includes a driving signal generation circuit, a gating circuit, an output control circuit, a voltage control circuit and an output circuit; the driving signal generation circuit generates the Nth stage of driving signal; the gating circuit writes a gating input signal into the first node under the control of a gating control signal; the output control circuit connects the first control node and the second node under the control of a potential of the first node; the voltage control circuit controls a potential of the second node according to the potential of the first node; the output circuit connects the output driving terminal and the first voltage terminal under the control of the potential of the second node, and connects the output driving terminal and the second voltage terminal under the control of the potential of the second control node; N is a positive integer.

Abstract: An application-level memory control group of a first application may be created when the first application is opened. An anonymous page of the first application is added to a least recently used linked list of the application-level memory control group, and a file page of the first application is added to a global least recently used linked list. An application-level memory control group is created in a dimension of an application, and an anonymous page of the application is managed in a refined manner. In addition, a file page of the application-level memory control group may be managed based on a global least recently used linked list.

Abstract: Various aspects of the present disclosure generally relate to wireless communication. In some aspects, a first user equipment (UE) may receive, from a second UE, a first message that indicates a sidelink bandwidth part (BWP) switch, for the second UE, to a first sidelink BWP, where the first message includes an indication of the first sidelink BWP and a first sidelink resource pool in the first sidelink BWP. The first UE may transmit, to the second UE, a second message that confirms the sidelink BWP switch for the second UE. The first UE may receive, from the second UE, a third message that activates the sidelink BWP switch, for the second UE, to the first sidelink BWP. Numerous other aspects are described.

Abstract: The present application discloses an access limiting method for a metadata server, an apparatus and a device, wherein the method is applied to a data lake metadata server, receives a metadata access request sent by a client, wherein the request is used for obtaining metadata stored by a storage server for describing target data, and the target data is data in a target table. The metadata service interface used by the data lake metadata server is determined according to the metadata access request. When the metadata service interface satisfies the preset condition, determining the number of applied tokens corresponding to the metadata access request according to the number of table partitions and the number of partition levels of the obtained target table.

Abstract: The present invention discloses a laser heating single-sensor fast scanning calorimeter, which comprises an FSC sample chamber, a chip sensor positioned in the FSC sample chamber and used for loading a sample, a laser heater for heating the sample, an infrared camera for shooting a sample image, a communication terminal and a control electronic element, wherein a perspective window serving as a light path channel is arranged in a center of the FSC sample chamber, and the laser heater and the infrared camera are positioned at the top of the perspective window; the infrared camera is connected with the communication terminal; one end of the control electronic element is connected with the communication terminal, and the other end of the control electronic element is connected with the laser heater and the chip sensor.

Abstract: The invention discloses a system for producing hydrogen by ammonia decomposition reaction and a hydrogen production method.

Abstract: Various aspects of the present disclosure generally relate to wireless communication. In some aspects, a first user equipment (UE) may generate information indicating a reference signal and a measurement report for a first sidelink between the first UE and a second UE. The first UE may use the information for a second sidelink between the first UE and the second UE. Numerous other aspects are described.

Abstract: The present disclosure provides a semiconductor device based on a dielectric material containing a metal interstitial impurity, including: a substrate, a dielectric material layer, and a functional layer. A material for preparing the dielectric material layer is a compound containing the metal interstitial impurity. The dielectric material layer and/or the functional layer is configured to subject to at least one of electricity, heat, light or magnetism, such that the dielectric material layer reaches a crystallization temperature to transit from a first state to a second state.

Abstract: Provided are a symmetric memory cell and a BNN circuit. The symmetric memory cell includes a first complementary structure and a second complementary structure, the second complementary structure being symmetrically connected to the first complementary structure in a first direction, wherein the first complementary structure includes a first control transistor configured to be connected to the second complementary structure, the second complementary structure includes a second control transistor, a drain electrode of the second control transistor and a drain electrode of the first control transistor being symmetrically arranged in the first direction and connected to a bit line, and the symmetric memory cell is configured to store a weight value 1 or 0.

Abstract: The present disclosure provides a pharmaceutical composition containing a therapeutically effective amount of furmonertinib or a pharmaceutically acceptable salt thereof and optionally a pharmaceutically acceptable carrier, and use of furmonertinib or a pharmaceutically acceptable salt thereof, or said pharmaceutical composition in manufacture of a medicament for treating and/or preventing a disease mediated by HER2 exon 20 insertion mutation and/or EGFR rare mutation. The pharmaceutical composition of the present disclosure shows an excellent therapeutic effect on disease mediated by HER2 exon 20 insertion mutation and/or EGFR rare mutation (for example, non-small cell lung cancer (NSCLC)) with little side effects and excellent safety.

Abstract: A downhole electromagnetic logging tool comprises a transmitting system, a magnetic field sensor array and a control module. The transmitting system and the magnetic field sensor array are both connected to the control module. The transmitting system comprises an upper emission coil and a lower emission coil, which are respectively arranged above and below the magnetic field sensor array, for generating magnetic fields of opposite polarities, allowing the magnetic fields to be concentrated at the magnetic field sensor array. A casing generates a secondary magnetic field, which is received by the magnetic field sensor array to complete detection of the casing.

Abstract: Disclosed is a neural network operation device, including: an operation array including operation units, wherein each operation unit includes: a source terminal, a drain terminal, a gate electrode, a threshold voltage adjustment layer under the gate electrode, and a channel region extending between a source region and a drain region, the threshold voltage adjustment layer is located on the channel region. The gate electrodes of each column of operation units of the operation array are connected together, and each column is used to adjust a weight value according to a threshold voltage adjusted by the threshold voltage adjustment layer. The threshold voltage adjustment layer is a ferroelectric layer.

Abstract: A writing method and erasing method of a fusion memory are provided, and the fusion memory includes a plurality of memory cells, and each memory cell of the plurality of memory cells includes a bulk substrate; a source and a drain on the bulk substrate, a channel region extending between the source and the drain, and a ferroelectric layer and a gate stacked on the channel region; and the writing method includes: applying a first voltage between the gate of at least one memory cell and the bulk of at least one memory cell, in which the first voltage is less than a reversal voltage at which the ferroelectric layer is polarization reversed, and each of the source and the drain is grounded or in a floating state.

Abstract: Provided are delayed sustained-release oral drug dosage forms comprising a Janus kinase (JAK) inhibitor, such as tofacitinib. In other aspects, provided are methods of designing, methods of making, such as using three-dimensional printing, and methods of treatment and/or prevention associated with the oral drug dosage forms described herein.

Abstract: A method of preparing a programmable diode, including: forming a tungsten plug by a standard CMOS process; taking the tungsten plug as a lower electrode and depositing a functional layer material such as a ferroelectric film on the tungsten plug; depositing an upper electrode on the functional layer material; and patterning the upper electrode and a functional layer to complete a preparation of the programmable diode. The present disclosure further discloses a ferroelectric memory of a programmable diode prepared by the method of preparing a programmable diode. The method of preparing a programmable diode does not require growing a lower electrode and reduces a complexity of the process. The ferroelectric memory includes a transistor and a programmable diode. This design stores information according to different polarities of the diode, thus a device area may be further reduced and a storage density may be improved.

Abstract: The present disclosure discloses a device and a method for testing fatigue characteristics of a selector (210). The device includes: a voltage divider (220) and a counter (103). The voltage divider (220) is connected to a selector (210) to be tested and is configured to divide a voltage for the selector (210) to be tested during a test process. The counter (103) is connected to the selector (210) to be tested and is configured to detect voltage and/or current changes of the selector (210) to be tested.

Abstract: A complementary storage unit and a method of preparing the same, and a complementary memory. The complementary storage unit includes: a control transistor, a pull-up diode and a pull-down diode. The control transistor is configured to control reading and writing of the storage unit. One end of the pull-up diode is connected to a positive selection line, and the other end thereof is connected to a source end of the control transistor, so as to control a high-level input. One end of the pull-down diode is connected to a negative selection line, and the other end thereof is connected to the source end of the control transistor, so as to control a low-level input. The pull-up diode and the pull-down diode are symmetrically arranged in a first direction.

Abstract: The present disclosure provides a fusion memory including a plurality of memory cells, wherein each memory cell of the plurality of memory cells includes: a bulk substrate; a source and a drain on the bulk substrate; a channel extending between the source and the drain; a ferroelectric layer on the channel; and a gate on the ferroelectric layer.

Abstract: Embodiments of the present disclosure relate to the field of semiconductors, and provide a semiconductor structure and a forming method thereof. The forming method includes: providing a substrate; performing first oxidation on a part of the substrate to form a first dielectric layer; and performing second oxidation on a part of the substrate just under the first dielectric layer to form a second dielectric layer, where the first dielectric layer and the second dielectric layer form a dielectric layer on the substrate; and an oxidation rate of the first oxidation to a substrate material is less than that of the second oxidation to the substrate material.