Abstract: A complementary storage unit and a method of preparing the same, and a complementary memory. The complementary storage unit includes: a control transistor, a pull-up diode and a pull-down diode. The control transistor is configured to control reading and writing of the storage unit. One end of the pull-up diode is connected to a positive selection line, and the other end thereof is connected to a source end of the control transistor, so as to control a high-level input. One end of the pull-down diode is connected to a negative selection line, and the other end thereof is connected to the source end of the control transistor, so as to control a low-level input. The pull-up diode and the pull-down diode are symmetrically arranged in a first direction.

Abstract: The present disclosure provides a semiconductor device based on a dielectric material containing a metal interstitial impurity, including: a substrate, a dielectric material layer, and a functional layer. A material for preparing the dielectric material layer is a compound containing the metal interstitial impurity. The dielectric material layer and/or the functional layer is configured to subject to at least one of electricity, heat, light or magnetism, such that the dielectric material layer reaches a crystallization temperature to transit from a first state to a second state.

Abstract: Provided are a symmetric memory cell and a BNN circuit. The symmetric memory cell includes a first complementary structure and a second complementary structure, the second complementary structure being symmetrically connected to the first complementary structure in a first direction, wherein the first complementary structure includes a first control transistor configured to be connected to the second complementary structure, the second complementary structure includes a second control transistor, a drain electrode of the second control transistor and a drain electrode of the first control transistor being symmetrically arranged in the first direction and connected to a bit line, and the symmetric memory cell is configured to store a weight value 1 or 0.

Abstract: A downhole electromagnetic logging tool comprises a transmitting system, a magnetic field sensor array and a control module. The transmitting system and the magnetic field sensor array are both connected to the control module. The transmitting system comprises an upper emission coil and a lower emission coil, which are respectively arranged above and below the magnetic field sensor array, for generating magnetic fields of opposite polarities, allowing the magnetic fields to be concentrated at the magnetic field sensor array. A casing generates a secondary magnetic field, which is received by the magnetic field sensor array to complete detection of the casing.

Abstract: Disclosed is a neural network operation device, including: an operation array including operation units, wherein each operation unit includes: a source terminal, a drain terminal, a gate electrode, a threshold voltage adjustment layer under the gate electrode, and a channel region extending between a source region and a drain region, the threshold voltage adjustment layer is located on the channel region. The gate electrodes of each column of operation units of the operation array are connected together, and each column is used to adjust a weight value according to a threshold voltage adjusted by the threshold voltage adjustment layer. The threshold voltage adjustment layer is a ferroelectric layer.

Abstract: A writing method and erasing method of a fusion memory are provided, and the fusion memory includes a plurality of memory cells, and each memory cell of the plurality of memory cells includes a bulk substrate; a source and a drain on the bulk substrate, a channel region extending between the source and the drain, and a ferroelectric layer and a gate stacked on the channel region; and the writing method includes: applying a first voltage between the gate of at least one memory cell and the bulk of at least one memory cell, in which the first voltage is less than a reversal voltage at which the ferroelectric layer is polarization reversed, and each of the source and the drain is grounded or in a floating state.

Abstract: Provided are delayed sustained-release oral drug dosage forms comprising a Janus kinase (JAK) inhibitor, such as tofacitinib. In other aspects, provided are methods of designing, methods of making, such as using three-dimensional printing, and methods of treatment and/or prevention associated with the oral drug dosage forms described herein.

Abstract: A method of preparing a programmable diode, including: forming a tungsten plug by a standard CMOS process; taking the tungsten plug as a lower electrode and depositing a functional layer material such as a ferroelectric film on the tungsten plug; depositing an upper electrode on the functional layer material; and patterning the upper electrode and a functional layer to complete a preparation of the programmable diode. The present disclosure further discloses a ferroelectric memory of a programmable diode prepared by the method of preparing a programmable diode. The method of preparing a programmable diode does not require growing a lower electrode and reduces a complexity of the process. The ferroelectric memory includes a transistor and a programmable diode. This design stores information according to different polarities of the diode, thus a device area may be further reduced and a storage density may be improved.

Abstract: The present disclosure discloses a device and a method for testing fatigue characteristics of a selector (210). The device includes: a voltage divider (220) and a counter (103). The voltage divider (220) is connected to a selector (210) to be tested and is configured to divide a voltage for the selector (210) to be tested during a test process. The counter (103) is connected to the selector (210) to be tested and is configured to detect voltage and/or current changes of the selector (210) to be tested.

Abstract: A complementary storage unit and a method of preparing the same, and a complementary memory. The complementary storage unit includes: a control transistor, a pull-up diode and a pull-down diode. The control transistor is configured to control reading and writing of the storage unit. One end of the pull-up diode is connected to a positive selection line, and the other end thereof is connected to a source end of the control transistor, so as to control a high-level input. One end of the pull-down diode is connected to a negative selection line, and the other end thereof is connected to the source end of the control transistor, so as to control a low-level input. The pull-up diode and the pull-down diode are symmetrically arranged in a first direction.

Abstract: The present disclosure provides a fusion memory including a plurality of memory cells, wherein each memory cell of the plurality of memory cells includes: a bulk substrate; a source and a drain on the bulk substrate; a channel extending between the source and the drain; a ferroelectric layer on the channel; and a gate on the ferroelectric layer.

Abstract: Embodiments of the present disclosure relate to the field of semiconductors, and provide a semiconductor structure and a forming method thereof. The forming method includes: providing a substrate; performing first oxidation on a part of the substrate to form a first dielectric layer; and performing second oxidation on a part of the substrate just under the first dielectric layer to form a second dielectric layer, where the first dielectric layer and the second dielectric layer form a dielectric layer on the substrate; and an oxidation rate of the first oxidation to a substrate material is less than that of the second oxidation to the substrate material.

Abstract: Provided are a symmetric memory cell and a BNN circuit. The symmetric memory cell includes a first complementary structure and a second complementary structure, the second complementary structure being symmetrically connected to the first complementary structure in a first direction, wherein the first complementary structure includes a first control transistor configured to be connected to the second complementary structure, the second complementary structure includes a second control transistor, a drain electrode of the second control transistor and a drain electrode of the first control transistor being symmetrically arranged in the first direction and connected to a bit line, and the symmetric memory cell is configured to store a weight value 1 or 0.

Abstract: A downhole electromagnetic logging tool comprises a transmitting system, a magnetic field sensor array and a control module. The transmitting system and the magnetic field sensor array are both connected to the control module. The transmitting system comprises an upper emission coil and a lower emission coil, which are respectively arranged above and below the magnetic field sensor array, for generating magnetic fields of opposite polarities, allowing the magnetic fields to be concentrated at the magnetic field sensor array. A casing generates a secondary magnetic field, which is received by the magnetic field sensor array to complete detection of the casing.

Abstract: The present disclosure provides a self-rectifying resistive memory, including: a lower electrode; a resistive material layer formed on the lower electrode and used as a storage medium; a barrier layer formed on the resistive material layer and using a semiconductor material or an insulating material; and an upper electrode formed on the barrier layer to achieve Schottky contact with the material of the barrier layer; wherein, the Schottky contact between the upper electrode and the material of the barrier layer is used to realize self-rectification of the self-rectifying resistive memory. Thus, no additional gate transistor or diode is required as the gate unit. In addition, because the device has self-rectifying characteristics, it is capable of suppressing read crosstalk in the cross-array.

Abstract: A method for forming a semiconductor structure includes: providing a substrate, in which a gate structure is formed on the substrate; forming first side walls covering side surfaces of the gate structure, in which the first side walls have a first preset thickness in a direction parallel to a plane of the substrate; performing first ion implantation on the substrate on both sides of the gate structure exposed to the first side walls; removing a part of the first side walls to form second side walls, in which the second side walls have a second preset thickness in the direction parallel to the plane of the substrate; and performing second ion implantation on the substrate on both sides of the gate structure, in which doping types of the first ion implantation and the second ion implantation are different.

Abstract: The present disclosure provides oral drug dosage forms comprising: (a) an erodible non-stimulant material admixed with an ADHD non-stimulant; and (b) an erodible stimulant material admixed with an ADHD stimulant, wherein the erodible non-stimulant material admixed with the ADHD non-stimulant is embedded in a substrate material, and wherein upon exposure to gastrointestinal fluid the ADHD non-stimulant is released according to a desired non-stimulant release profile and the ADHD stimulant is released according to a desired stimulant release profile. In some embodiment, the ADHD non-stimulant is released according to a sustained release profile. In some embodiments, the ADHD stimulant is released according to an immediate release profile. The oral drug dosage forms of the present disclosure are useful for the treatment of attention deficit hyperactivity disorder (ADHD). Also provided herein are methods of designing and manufacturing the oral drug dosage forms described herein.

Abstract: A HfO2-based ferroelectric capacitor and a preparation method therefor, and a HfO2-based ferroelectric memory, relating to the technical field of microelectronics. The purpose of enlarging the memory window of the ferroelectric memory is achieved by inserting an Al2O3 intercalation layer having a coefficient of thermal expansion smaller than TiN between a dielectric layer and an upper electrode (TiN) of the ferroelectric capacitor. The HfO2-based ferroelectric capacitor comprises a substrate layer, a lower electrode, a dielectric layer, an Al2O3 intercalation layer, an upper electrode and a metal protection layer from bottom to top. The memory window can be increased, information misreading is effectively prevented, and therefore, the reliability of the memory is improved.

Abstract: A control method includes sending, by a controller, a created context-aware model to a context-aware engine. The context-aware model is used to define a preset control performed when target data meets a trigger condition and to instruct the context-aware engine to send indication information to the controller when the context-aware engine determines that the target data meets the trigger condition. The preset control is used to implement a context-aware function. The indication information is used to indicate that the target data meets the trigger condition. The method also includes receiving, by the controller, the indication information. The method further includes performing, by the controller, the preset control based on the indication information.

Abstract: The disclosure discloses a selector and a preparation method thereof. The selector includes: a substrate 1; an alternating layer 2 provided on the substrate 1, the alternating layer 2 being alternately formed by a bottom electrode layer 21 and an insulating layer 22; the alternating layer 2 is provided with a U-shaped groove; a selective layer 3 and a dielectric layer 4 being sequentially deposited in a direction from an inner wall of the U-shaped groove to a center of the U-shaped groove; and a top electrode layer 5 is filled in a concave space defined by the dielectric layer 4. The selector and the preparation method according to one or more embodiments of the disclosure can address the technical problem of high leakage current of the selector in existing technology and provide a selector with low leakage current.