Patents by Inventor Qing Luo
Qing Luo has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20220172035Abstract: Disclosed is a neural network operation device, including: an operation array including operation units, wherein each operation unit includes: a source terminal, a drain terminal, a gate electrode, a threshold voltage adjustment layer under the gate electrode, and a channel region extending between a source region and a drain region, the threshold voltage adjustment layer is located on the channel region. The gate electrodes of each column of operation units of the operation array are connected together, and each column is used to adjust a weight value according to a threshold voltage adjusted by the threshold voltage adjustment layer. The threshold voltage adjustment layer is a ferroelectric layer.Type: ApplicationFiled: January 28, 2019Publication date: June 2, 2022Inventors: Hangbing LV, Xiaoxin XU, Qing LUO, Ming LIU
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Patent number: 11328411Abstract: Systems and methods for detecting defects on a reticle are provided. One system includes computer subsystem(s) configured for performing at least one repeater defect detection step in front-end processing during an inspection process performed on a wafer having features printed in a lithography process using a reticle. The at least one repeater defect detection step performed in the front-end processing includes identifying any defects detected at corresponding locations in two or more test images by double detection and any defects detected by stacked defect detection as first repeater defect candidates. One or more additional repeater defect detections may be performed on the first repeater defect candidates to generate final repeater defect candidates and identify defects on the reticle from the final repeater defect candidates.Type: GrantFiled: April 30, 2021Date of Patent: May 10, 2022Assignee: KLA Corp.Inventors: Hong Chen, Kenong Wu, Xiaochun Li, James A. Smith, Eugene Shifrin, Qing Luo, Michael Cook, Wei Si, Leon Yu, Bjorn Brauer, Nurmohammed Patwary, Ramon Ynzunza, Neil Troy
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Publication number: 20220122997Abstract: Disclosed is a memory, including a plurality of memory units, wherein each memory unit includes: a bulk substrate; a source electrode, a drain electrode and a channel region extending between a source region and a drain region that are located on the bulk substrate; a deep-level defect dielectric layer on the channel region; and a gate electrode on the deep-level defect dielectric layer. The memory of the present disclosure allows the memory unit to operate in the charge trapping mode and the polarization inversion mode. Therefore, the memory has functions of both DRAM and NAND, and combines the advantages of the two.Type: ApplicationFiled: January 28, 2019Publication date: April 21, 2022Inventors: Hangbing LV, Qing LUO, Xiaoxin XU, Tiancheng GONG, Ming LIU
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Publication number: 20220115052Abstract: A writing method and erasing method of a fusion memory are provided, and the fusion memory includes a plurality of memory cells, and each memory cell of the plurality of memory cells includes a bulk substrate; a source and a drain on the bulk substrate, a channel region extending between the source and the drain, and a ferroelectric layer and a gate stacked on the channel region; and the writing method includes: applying a first voltage between the gate of at least one memory cell and the bulk of at least one memory cell, in which the first voltage is less than a reversal voltage at which the ferroelectric layer is polarization reversed, and each of the source and the drain is grounded or in a floating state.Type: ApplicationFiled: January 28, 2019Publication date: April 14, 2022Inventors: Hangbing LV, Qing LUO, Xiaoxin XU, Tiancheng GONG, Ming LIU
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Publication number: 20220093150Abstract: The present disclosure provides a fusion memory including a plurality of memory cells, wherein each memory cell of the plurality of memory cells includes: a bulk substrate; a source and a drain on the bulk substrate; a channel extending between the source and the drain; a ferroelectric layer on the channel; and a gate on the ferroelectric layer.Type: ApplicationFiled: January 28, 2019Publication date: March 24, 2022Inventors: Hangbing Lv, Qing Luo, Xiaoxin Xu, Tiancheng Gong, Ming Liu
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Patent number: 11205750Abstract: The present disclosure provides a 1S1R memory integrated structure and a method for fabricating the same, wherein the 1S1R memory integrated structure includes: a word line metal, a resistive material layer, a selector lower electrode, a selector material layer, a selector upper electrode, an interconnection wire, and a bit line metal; wherein the selector material layer is in a shape of a groove, and the selector upper electrode is formed in the groove. According to the 1S1R memory integrated structure and its fabricating method in the present disclosure, by the change of the integrated position of the selector, the device area of the selector is much larger than the device area of the memory, which significantly reduces the requirement for the on-state current density of the selector.Type: GrantFiled: February 10, 2020Date of Patent: December 21, 2021Assignee: Institute of Microelectronics Chinese Academy of SciencesInventors: Qing Luo, Hangbing Lv, Ming Liu, Xiaoxin Xu, Cheng Lu
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Publication number: 20210342992Abstract: Systems and methods for detecting defects on a reticle are provided. One system includes computer subsystem(s) configured for performing at least one repeater defect detection step in front-end processing during an inspection process performed on a wafer having features printed in a lithography process using a reticle. The at least one repeater defect detection step performed in the front-end processing includes identifying any defects detected at corresponding locations in two or more test images by double detection and any defects detected by stacked defect detection as first repeater defect candidates. One or more additional repeater defect detections may be performed on the first repeater defect candidates to generate final repeater defect candidates and identify defects on the reticle from the final repeater defect candidates.Type: ApplicationFiled: April 30, 2021Publication date: November 4, 2021Inventors: Hong Chen, Kenong Wu, Xiaochun Li, James A. Smith, Eugene Shifrin, Qing Luo, Michael Cook, Wei Si, Leon Yu, Bjorn Brauer, Nurmohammed Patwary, Ramon Ynzunza, Neil Troy
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Patent number: 11085792Abstract: A method for determining an estimated time of arrival (ETA) includes receiving a start location and a destination from a user device via a network. The method also includes obtaining a machine learning model for determining an ETA, which is generated according to a process including: obtaining historical data related to an on-demand service order; determining a high-dimensional sparse feature based on the historical data; and determining a machine learning model based on the high-dimensional sparse feature. The method further includes determining an ETA for a target route based on the machine learning model, the start location, and the destination, and transmitting the determined ETA to the user device via the network.Type: GrantFiled: November 15, 2019Date of Patent: August 10, 2021Assignee: BEIJING DIDI INFINITY TECHNOLOGY AND DEVELOPMENT CO., LTD.Inventors: Zhiyuan Zhong, Qing Luo, Zheng Wang
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Publication number: 20210077410Abstract: The present disclosure provides oral drug dosage forms comprising: (a) an erodible non-stimulant material admixed with an ADHD non-stimulant; and (b) an erodible stimulant material admixed with an ADHD stimulant, wherein the erodible non-stimulant material admixed with the ADHD non-stimulant is embedded in a substrate material, and wherein upon exposure to gastrointestinal fluid the ADHD non-stimulant is released according to a desired non-stimulant release profile and the ADHD stimulant is released according to a desired stimulant release profile. In some embodiment, the ADHD non-stimulant is released according to a sustained release profile. In some embodiments, the ADHD stimulant is released according to an immediate release profile. The oral drug dosage forms of the present disclosure are useful for the treatment of attention deficit hyperactivity disorder (ADHD). Also provided herein are methods of designing and manufacturing the oral drug dosage forms described herein.Type: ApplicationFiled: December 25, 2018Publication date: March 18, 2021Inventors: Feihuang DENG, Xiaoling LI, Senping CHENG, Ying WANG, Qing LUO
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Publication number: 20210013404Abstract: The present disclosure provides a self-rectifying resistive memory, including: a lower electrode; a resistive material layer formed on the lower electrode and used as a storage medium; a barrier layer formed on the resistive material layer and using a semiconductor material or an insulating material; and an upper electrode formed on the barrier layer to achieve Schottky contact with the material of the barrier layer; wherein, the Schottky contact between the upper electrode and the material of the barrier layer is used to realize self-rectification of the self-rectifying resistive memory. Thus, no additional gate transistor or diode is required as the gate unit. In addition, because the device has self-rectifying characteristics, it is capable of suppressing read crosstalk in the cross-array.Type: ApplicationFiled: March 28, 2018Publication date: January 14, 2021Inventors: Qing LUO, Hangbing LV, Ming LIU
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Patent number: 10817154Abstract: A system and method for processing a screenshot-type note of a streaming document. The system comprises: a gesture processing module (110) for recording screen coordinates of a selected region in a pre-set shape determined by a gesture in a current page of the streaming document; a note position calculation module (120) for receiving the screen coordinates of the selected region in the pre-set shape, and converting a screen coordinate of a pre-set position in the selected region into a relative position of a leaf node in the streaming document; and a note information storage module (130) for storing the relative position of the leaf node and the screen coordinates of the selected region as note position information. The technical solution can improve the accuracy of a display position of a screenshot-type note in a streaming document.Type: GrantFiled: April 12, 2017Date of Patent: October 27, 2020Assignees: BEIJING JINGDONG SHANGKE INFORMATION TECHNOLOGY CO., LTD., BEIJING JINGDONG CENTURY TRADING CO., LTD.Inventors: Tienan Jiang, Qing Luo
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Patent number: 10720578Abstract: Provided are a self-gating resistive storage device and a method for fabrication thereof; said self-gating resistive storage device comprises: lower electrodes; insulating dielectric layers arranged perpendicular to, and intersecting with, the lower electrodes to form a stacked structure, said stacked structure being provided with a vertical trench; a gating layer grown on the lower electrodes by means of self-alignment technique, the interlayer leakage channel running through the gating layer being isolated via the insulating dielectric layers; a resistance transition layer arranged in the vertical trench and connected to the insulating dielectric layers and the gating layer; and an upper electrode arranged in the resistance transition layer.Type: GrantFiled: April 29, 2016Date of Patent: July 21, 2020Assignee: THE INSTITUTE OF MICROELECTRONICS OF CHINESE ACADEMY OF SCIENCESInventors: Hangbing LV, Ming Liu, Xiaoxin Xu, Qing Luo, Qi Liu, Shibing Long
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Publication number: 20200176674Abstract: The present disclosure provides a 1S1R memory integrated structure and a method for fabricating the same, wherein the 1S1R memory integrated structure includes: a word line metal, a resistive material layer, a selector lower electrode, a selector material layer, a selector upper electrode, an interconnection wire, and a bit line metal; wherein the selector material layer is in a shape of a groove, and the selector upper electrode is formed in the groove. According to the 1S1R memory integrated structure and its fabricating method in the present disclosure, by the change of the integrated position of the selector, the device area of the selector is much larger than the device area of the memory, which significantly reduces the requirement for the on-state current density of the selector.Type: ApplicationFiled: February 10, 2020Publication date: June 4, 2020Inventors: Qing Luo, Hangbing Lv, Ming Liu, Xiaoxin Xu, Cheng Lu
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Patent number: 10665780Abstract: A selector for a bipolar resistive random access memory and a method for fabricating the selector are provided. The method includes: providing a substrate; forming a lower electrode on the substrate, where the lower electrode is made of a metal, and the metal is made up of metal atoms which diffuse under an annealing condition of below 400° C.; forming a first metal oxide layer on the lower electrode; performing an annealing process on the first metal oxide layer to make the metal atoms in the lower electrode diffuse into the first metal oxide layer to form a first metal oxide layer doped with metal atoms; forming a second metal oxide layer on the first metal oxide layer doped with metal atoms; forming an upper electrode layer on the second metal oxide layer; and patterning the upper electrode layer to form an upper electrode.Type: GrantFiled: March 18, 2016Date of Patent: May 26, 2020Assignee: INSTITUTE OF MICROELECTRONICS, CHINESE ACADEMY OF SCIENCESInventors: Ming Liu, Qing Luo, Xiaoxin Xu, Hangbing Lv, Shibing Long, Qi Liu
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Publication number: 20200133217Abstract: A control method includes sending, by a controller, a created context-aware model to a context-aware engine. The context-aware model is used to define a preset control performed when target data meets a trigger condition and to instruct the context-aware engine to send indication information to the controller when the context-aware engine determines that the target data meets the trigger condition. The preset control is used to implement a context-aware function. The indication information is used to indicate that the target data meets the trigger condition. The method also includes receiving, by the controller, the indication information. The method further includes performing, by the controller, the preset control based on the indication information.Type: ApplicationFiled: December 30, 2019Publication date: April 30, 2020Inventors: Xiaotao DENG, Qing LUO, Zhifeng CHEN, Tao HAN, Junfei ZENG
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Patent number: 10604785Abstract: An unprecedented mechanism of ubiquitination that is independent of E1 and E2 enzymes, instead relying on activation of ubiquitin by ADP-ribosylation, and which is mediated by members of the SidE effector family encoded by the bacterial pathogen Legionella pneumophila is disclosed. The herein disclosed method demonstrates a method in which ubiquitination can be carried out by a single enzyme. In addition, the present disclosure also provides compositions that may be used in ubiquitination assays and/or methods of screening active substance that may inhibit the ubiquitination process.Type: GrantFiled: April 4, 2017Date of Patent: March 31, 2020Assignee: Purdue Research FoundationInventors: Zhao-Qing Luo, Jiazhang Qiu, Chittaranjan Das, Michael Sheedlo
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Publication number: 20200096361Abstract: A method for determining an estimated time of arrival (ETA) includes receiving a start location and a destination from a user device via a network. The method also includes obtaining a machine learning model for determining an ETA, which is generated according to a process including: obtaining historical data related to an on-demand service order; determining a high-dimensional sparse feature based on the historical data; and determining a machine learning model based on the high-dimensional sparse feature. The method further includes determining an ETA for a target route based on the machine learning model, the start location, and the destination, and transmitting the determined ETA to the user device via the network.Type: ApplicationFiled: November 15, 2019Publication date: March 26, 2020Applicant: BEIJING DIDI INFINITY TECHNOLOGY AND DEVELOPMENT CO., LTD.Inventors: Zhiyuan ZHONG, Qing LUO, Zheng WANG
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Publication number: 20200058704Abstract: A transition metal oxide based selector, a method for preparing the same and resistive random access memory are provided. The method comprises: S1, forming a tungsten plug on a transistor; S2, using the tungsten plug to function as a lower electrode, and preparing a transition metal layer on the tungsten plug; S3, oxidizing the transition metal layer to convert the transition metal layer into a transition metal oxide layer; and S4, depositing an upper electrode on the transition metal oxide, patterning the upper electrode and the transition metal oxide. The selector of the present disclosure may provide a high current density and has a good uniformity. The formed 1S1R structure may effectively eliminate crosstalk phenomenon in a resistive random access memory array, and effectively increase the storage density without increasing the storage unit area, thereby increasing device integration.Type: ApplicationFiled: February 22, 2017Publication date: February 20, 2020Applicant: INSTITUTE OF MICROELECTRONICS, CHINESE ACADEMY OF SCIENCESInventors: Hangbing LV, Qing LUO, Xiaoxin XU, Shibing LONG, Qi LIU, Ming LIU
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Publication number: 20190188818Abstract: A method for determining an estimated time of arrival (ETA) may include obtaining a service request from a terminal and determining a reference image relating to the service request. The method may also include obtaining a trained neural network model. The method may further include determining an ETA relating to the service request based on the reference image and the trained neural network model, and transmitting the ETA to the terminal.Type: ApplicationFiled: December 30, 2018Publication date: June 20, 2019Applicant: BEIJING DIDI INFINITY TECHNOLOGY AND DEVELOPMENT CO., LTD.Inventors: Qing LUO, Zheng WANG
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Patent number: 10320477Abstract: A system and method for automatic discovery of an optical cable route. The method comprises: a light source power meter automatically monitoring an attenuation value of an optical cable fiber core, the optical cable fiber core being configured in an optical cable route; when the power meter generates an alarm, determining a level of the optical power alarm and reporting the alarm condition of the optical cable route in real time; and a drive automatically searching for available optical cable routes to provide options of available optical cable routes for real-time allocation of services.Type: GrantFiled: December 15, 2015Date of Patent: June 11, 2019Assignee: Accelink Technologies Co., Ltd.Inventors: Shizhan Yu, Quanzhong Zhang, Falong Liu, Qing Luo, Zhizhu Zhou, Jiekui Yu