Abstract: An integrated circuit containing an extended drain MOS transistor may be formed by forming a drift region implant mask with mask fingers abutting a channel region and extending to the source/channel active area, but not extending to a drain contact active area. Dopants implanted through the exposed fingers form lateral doping striations in the substrate under the mask fingers. An average doping density of the drift region under the gate is at least 25 percent less than an average doping density of the drift region at the drain contact active area. In one embodiment, the dopants diffuse laterally to form a continuous drift region. In another embodiment, substrate material between lateral doping striations remains an opposite conductivity type from the lateral doping striations.

Abstract: An integrated circuit containing an extended drain MOS transistor may be formed by forming a drift region implant mask with mask fingers abutting a channel region and extending to the source/channel active area, but not extending to a drain contact active area. Dopants implanted through the exposed fingers form lateral doping striations in the substrate under the mask fingers. An average doping density of the drift region under the gate is at least 25 percent less than an average doping density of the drift region at the drain contact active area. In one embodiment, the dopants diffuse laterally to form a continuous drift region. In another embodiment, substrate material between lateral doping striations remains an opposite conductivity type from the lateral doping striations.

Abstract: Embodiments provide a method and device for electrically monitoring trench depths in semiconductor devices. To electrically measure a trench depth, a pinch resistor can be formed in a deep well region on a semiconductor substrate. A trench can then be formed in the pinch resistor. The trench depth can be determined by an electrical test of the pinch resistor. The disclosed method and device can provide statistical data analysis across a wafer and can be implemented in production scribe lanes as a process monitor. The disclosed method can also be useful for determining device performance of LDMOS transistors. The on-state resistance (Rdson) of the LDMOS transistors can be correlated to the electrical measurement of the trench depth.

Abstract: A method for forming a bipolar transistor device includes providing a semiconductor substrate. An oxide layer is formed on the semiconductor substrate. The oxide layer is patterned to form an opening that exposes a portion of the semiconductor substrate. A dopant, such as antimony, is implanted into the semiconductor substrate through the opening to form a buried layer. An upper portion of the mask layer is removed to define a thin mask layer. A buried layer diffusion process is performed to drive in the implanted dopants while mitigating recess formation.

Abstract: Exemplary embodiments provide manufacturing methods for forming a doped region in a semiconductor. Specifically, the doped region can be formed by multiple ion implantation processes using a patterned photoresist (PR) layer as a mask. The patterned PR layer can be formed using a hard-bakeless photolithography process by removing a hard-bake step to improve the profile of the patterned PR layer. The multiple ion implantation processes can be performed in a sequence of, implanting a first dopant species using a high energy; implanting the first dopant species using a reduced energy and an increased implant angle (e.g., about 9° or higher); and implanting a second dopant species using a reduced energy. In various embodiments, the doped region can be used as a double diffused region for LDMOS transistors.

Abstract: Exemplary embodiments provide manufacturing methods for forming a doped region in a semiconductor. Specifically, the doped region can be formed by multiple ion implantation processes using a patterned photoresist (PR) layer as a mask. The patterned PR layer can be formed using a hard-bakeless photolithography process by removing a hard-bake step to improve the profile of the patterned PR layer. The multiple ion implantation processes can be performed in a sequence of, implanting a first dopant species using a high energy; implanting the first dopant species using a reduced energy and an increased implant angle (e.g., about 90 or higher); and implanting a second dopant species using a reduced energy. In various embodiments, the doped region can be used as a double diffused region for LDMOS transistors.

Abstract: Embodiments provide a method and device for electrically monitoring trench depths in semiconductor devices. To electrically measure a trench depth, a pinch resistor can be formed in a deep well region on a semiconductor substrate. A trench can then be formed in the pinch resistor. The trench depth can be determined by an electrical test of the pinch resistor. The disclosed method and device can provide statistical data analysis across a wafer and can be implemented in production scribe lanes as a process monitor. The disclosed method can also be useful for determining device performance of LDMOS transistors. The on-state resistance (Rdson) of the LDMOS transistors can be correlated to the electrical measurement of the trench depth.

Abstract: A method for forming a bipolar transistor device includes providing a semiconductor substrate. An oxide layer is formed on the semiconductor substrate. The oxide layer is patterned to form an opening that exposes a portion of the semiconductor substrate. A dopant, such as antimony, is implanted into the semiconductor substrate through the opening to form a buried layer. An upper portion of the mask layer is removed to define a thin mask layer. A buried layer diffusion process is performed to drive in the implanted dopants while mitigating recess formation.

Abstract: The present invention provides a method for monitoring a shift in a buried layer in a semiconductor device. The method for monitoring the shift in the buried layer, among other steps, includes forming a buried layer test structure in, on or over a substrate of a semiconductor device, the buried layer test structure including a first test buried layer located in or on the substrate, the first test buried layer shifted a predetermined distance with respect to a first test feature. The buried layer test structure further includes a second test buried layer lodated in the substrate, the second test buried layer shifted a predetermined but different distance with respect to a second test feature. The method for monitoring the shift in the buried layer may further include applying a test signal to the buried layer test structure to determine an actual shift relative to the predetermined shift.

Abstract: The present invention provides a method for monitoring a shift in a buried layer in a semiconductor device and a method for manufacturing an integrated circuit using the method for monitoring the shift in the buried layer. The method for monitoring the shift in the buried layer, among other steps, includes forming a buried layer test structure (200) in, on or over a substrate (210) of a semiconductor device, the buried layer test structure (200) including a first test buried layer (230a) located in or on the substrate (210), the first test buried layer (230a) shifted a predetermined distance with respect to a first test feature (240a). The buried layer test structure (200) further includes a second test buried layer (230b) located in the substrate (210), the second test buried layer (23b) shifted a predetermined but different distance with respect to a second test feature (240b).

Abstract: The present invention relates to a method for forming cobalt disilicide structure on a silicon substrate comprising the steps of depositing a cobalt layer on the substrate, thereafter depositing a refractory metal on the cobalt layer, thereby forming a bilayer structure on the said substrate, and heating the bilayer structure. The present invention also relates to a method for forming self-aligned cobalt disilicide on a metal oxide semiconductor transistor with a source drain and gate regions in a silicon substrate comprising the steps of: depositing a cobalt layer on the substrate, thereafter depositing a refractory metal layer on the cobalt layer, heating the silicon substrate, thereby forming a cobalt dislicide layer on the gate, source, and drain regions of the MOS transistor, and selectively etching the remaining nonsilicide cobalt and refractory metal from the substrate except from the source, drain, and gate regions.