Patents by Inventor Qingfeng Wang
Qingfeng Wang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20200404574Abstract: During disclosed communication techniques, an electronic device (such as an access point) may receive one or more packets from another electronic device, where the other electronic device has an established connection or association with the electronic device, and the one or more packets are communicated using a first band of frequencies. Then, the electronic device may determine to recommend a basic service set (BSS) transition from the first band of frequencies to at least a second band of frequencies. Moreover, the electronic device may provide a request packet to the other electronic device with a recommendation with one or more candidates for the BSS transition, such as a channel in the second band of frequencies. Next, the electronic device may receive a response packet from the other electronic device, where the response packet indicates a remedial action of the other electronic device in response to the request packet.Type: ApplicationFiled: September 4, 2020Publication date: December 24, 2020Applicant: ARRIS Enterprises LLCInventors: Wen Chen, Wenge Ren, Qingfeng Wang
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Patent number: 10820256Abstract: During disclosed communication techniques, an electronic device (such as an access point) may receive one or more packets from another electronic device, where the other electronic device has an established connection or association with the electronic device, and the one or more packets are communicated using a first band of frequencies. Then, the electronic device may determine to recommend a basic service set (BSS) transition from the first band of frequencies to at least a second band of frequencies. Moreover, the electronic device may provide a request packet to the other electronic device with a recommendation with one or more candidates for the BSS transition, such as a channel in the second band of frequencies. Next, the electronic device may receive a response packet from the other electronic device, where the response packet indicates a remedial action of the other electronic device in response to the request packet.Type: GrantFiled: October 1, 2018Date of Patent: October 27, 2020Assignee: ARRIS Enterprises LLCInventors: Wen Chen, Wenge Ren, Qingfeng Wang
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Publication number: 20200107243Abstract: During disclosed communication techniques, an electronic device (such as an access point) may receive one or more packets from another electronic device, where the other electronic device has an established connection or association with the electronic device, and the one or more packets are communicated using a first band of frequencies. Then, the electronic device may determine to recommend a basic service set (BSS) transition from the first band of frequencies to at least a second band of frequencies. Moreover, the electronic device may provide a request packet to the other electronic device with a recommendation with one or more candidates for the BSS transition, such as a channel in the second band of frequencies. Next, the electronic device may receive a response packet from the other electronic device, where the response packet indicates a remedial action of the other electronic device in response to the request packet.Type: ApplicationFiled: October 1, 2018Publication date: April 2, 2020Inventors: Wen Chen, Wenge Ren, Qingfeng Wang
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Publication number: 20190373507Abstract: During operation, an access point communicates with one or more electronic devices. Based at least on the communication, the access point determines an available capacity metric of the access point. Then, the access point provides the determined available capacity metric to one or more second access points, and receives available capacity metrics of the one or more second access points. Moreover, the access point compares the available capacity metric and a parameter corresponding to the available capacity metrics. Based at least in part on the comparison, the access point dynamically and selectively performs load balancing, where performing the load balancing involves providing a recommendation to at least a first electronic device of the one or more electronic devices, and where the recommendation indicates that the first electronic device, which is associated with the access point, transition to a different communication channel.Type: ApplicationFiled: May 30, 2019Publication date: December 5, 2019Inventors: Wen Chen, Qingfeng Wang, Raghavendra Sadaramachandra
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Patent number: 8530296Abstract: An integrated circuit containing an extended drain MOS transistor may be formed by forming a drift region implant mask with mask fingers abutting a channel region and extending to the source/channel active area, but not extending to a drain contact active area. Dopants implanted through the exposed fingers form lateral doping striations in the substrate under the mask fingers. An average doping density of the drift region under the gate is at least 25 percent less than an average doping density of the drift region at the drain contact active area. In one embodiment, the dopants diffuse laterally to form a continuous drift region. In another embodiment, substrate material between lateral doping striations remains an opposite conductivity type from the lateral doping striations.Type: GrantFiled: February 12, 2013Date of Patent: September 10, 2013Assignee: Texas Instruments IncorporatedInventors: Pinghai Hao, Sameer Pendharkar, Binghua Hu, Qingfeng Wang
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Patent number: 8399924Abstract: An integrated circuit containing an extended drain MOS transistor may be formed by forming a drift region implant mask with mask fingers abutting a channel region and extending to the source/channel active area, but not extending to a drain contact active area. Dopants implanted through the exposed fingers form lateral doping striations in the substrate under the mask fingers. An average doping density of the drift region under the gate is at least 25 percent less than an average doping density of the drift region at the drain contact active area. In one embodiment, the dopants diffuse laterally to form a continuous drift region. In another embodiment, substrate material between lateral doping striations remains an opposite conductivity type from the lateral doping striations.Type: GrantFiled: June 15, 2011Date of Patent: March 19, 2013Assignee: Texas Instruments IncorporatedInventors: Pinghai Hao, Sameer Pendharkar, Binghua Hu, Qingfeng Wang
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Publication number: 20110309440Abstract: An integrated circuit containing an extended drain MOS transistor may be formed by forming a drift region implant mask with mask fingers abutting a channel region and extending to the source/channel active area, but not extending to a drain contact active area. Dopants implanted through the exposed fingers form lateral doping striations in the substrate under the mask fingers. An average doping density of the drift region under the gate is at least 25 percent less than an average doping density of the drift region at the drain contact active area. In one embodiment, the dopants diffuse laterally to form a continuous drift region. In another embodiment, substrate material between lateral doping striations remains an opposite conductivity type from the lateral doping striations.Type: ApplicationFiled: June 15, 2011Publication date: December 22, 2011Applicant: TEXAS INSTRUMENTS INCORPORATEDInventors: Pinghai Hao, Sameer Pendharkar, Binghua Hu, Qingfeng Wang
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Patent number: 7989232Abstract: Embodiments provide a method and device for electrically monitoring trench depths in semiconductor devices. To electrically measure a trench depth, a pinch resistor can be formed in a deep well region on a semiconductor substrate. A trench can then be formed in the pinch resistor. The trench depth can be determined by an electrical test of the pinch resistor. The disclosed method and device can provide statistical data analysis across a wafer and can be implemented in production scribe lanes as a process monitor. The disclosed method can also be useful for determining device performance of LDMOS transistors. The on-state resistance (Rdson) of the LDMOS transistors can be correlated to the electrical measurement of the trench depth.Type: GrantFiled: September 12, 2006Date of Patent: August 2, 2011Assignee: Texas Instruments IncorporatedInventors: Qingfeng Wang, Sameer P. Pendharkar, Binghua Hu
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Patent number: 7785974Abstract: A method for forming a bipolar transistor device includes providing a semiconductor substrate. An oxide layer is formed on the semiconductor substrate. The oxide layer is patterned to form an opening that exposes a portion of the semiconductor substrate. A dopant, such as antimony, is implanted into the semiconductor substrate through the opening to form a buried layer. An upper portion of the mask layer is removed to define a thin mask layer. A buried layer diffusion process is performed to drive in the implanted dopants while mitigating recess formation.Type: GrantFiled: June 26, 2006Date of Patent: August 31, 2010Assignee: Texas Instruments IncorporatedInventors: Binghua Hu, Yu-En Hsu, Qingfeng Wang
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Patent number: 7713825Abstract: Exemplary embodiments provide manufacturing methods for forming a doped region in a semiconductor. Specifically, the doped region can be formed by multiple ion implantation processes using a patterned photoresist (PR) layer as a mask. The patterned PR layer can be formed using a hard-bakeless photolithography process by removing a hard-bake step to improve the profile of the patterned PR layer. The multiple ion implantation processes can be performed in a sequence of, implanting a first dopant species using a high energy; implanting the first dopant species using a reduced energy and an increased implant angle (e.g., about 9° or higher); and implanting a second dopant species using a reduced energy. In various embodiments, the doped region can be used as a double diffused region for LDMOS transistors.Type: GrantFiled: May 25, 2007Date of Patent: May 11, 2010Assignee: Texas Instruments IncorporatedInventors: Binghua Hu, Sameer P. Pendharkar, Bill A. Wofford, Qingfeng Wang
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Publication number: 20080293206Abstract: Exemplary embodiments provide manufacturing methods for forming a doped region in a semiconductor. Specifically, the doped region can be formed by multiple ion implantation processes using a patterned photoresist (PR) layer as a mask. The patterned PR layer can be formed using a hard-bakeless photolithography process by removing a hard-bake step to improve the profile of the patterned PR layer. The multiple ion implantation processes can be performed in a sequence of, implanting a first dopant species using a high energy; implanting the first dopant species using a reduced energy and an increased implant angle (e.g., about 90 or higher); and implanting a second dopant species using a reduced energy. In various embodiments, the doped region can be used as a double diffused region for LDMOS transistors.Type: ApplicationFiled: May 25, 2007Publication date: November 27, 2008Inventors: Binghua Hu, Sameer P. Pendharkar, Bill A. Wofford, Qingfeng Wang
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Publication number: 20080085569Abstract: Embodiments provide a method and device for electrically monitoring trench depths in semiconductor devices. To electrically measure a trench depth, a pinch resistor can be formed in a deep well region on a semiconductor substrate. A trench can then be formed in the pinch resistor. The trench depth can be determined by an electrical test of the pinch resistor. The disclosed method and device can provide statistical data analysis across a wafer and can be implemented in production scribe lanes as a process monitor. The disclosed method can also be useful for determining device performance of LDMOS transistors. The on-state resistance (Rdson) of the LDMOS transistors can be correlated to the electrical measurement of the trench depth.Type: ApplicationFiled: September 12, 2006Publication date: April 10, 2008Inventors: Qingfeng Wang, Sameer P. Pendharkar, Binghua Hu
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Publication number: 20070298579Abstract: A method for forming a bipolar transistor device includes providing a semiconductor substrate. An oxide layer is formed on the semiconductor substrate. The oxide layer is patterned to form an opening that exposes a portion of the semiconductor substrate. A dopant, such as antimony, is implanted into the semiconductor substrate through the opening to form a buried layer. An upper portion of the mask layer is removed to define a thin mask layer. A buried layer diffusion process is performed to drive in the implanted dopants while mitigating recess formation.Type: ApplicationFiled: June 26, 2006Publication date: December 27, 2007Inventors: Binghua Hu, Yu-En Hsu, Qingfeng Wang
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Patent number: 7112953Abstract: The present invention provides a method for monitoring a shift in a buried layer in a semiconductor device. The method for monitoring the shift in the buried layer, among other steps, includes forming a buried layer test structure in, on or over a substrate of a semiconductor device, the buried layer test structure including a first test buried layer located in or on the substrate, the first test buried layer shifted a predetermined distance with respect to a first test feature. The buried layer test structure further includes a second test buried layer lodated in the substrate, the second test buried layer shifted a predetermined but different distance with respect to a second test feature. The method for monitoring the shift in the buried layer may further include applying a test signal to the buried layer test structure to determine an actual shift relative to the predetermined shift.Type: GrantFiled: February 2, 2005Date of Patent: September 26, 2006Assignee: Texas Instruments IncorporatedInventors: Xinfen Chen, Xiaoju Wu, John K. Arch, Qingfeng Wang
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Publication number: 20060038553Abstract: The present invention provides a method for monitoring a shift in a buried layer in a semiconductor device and a method for manufacturing an integrated circuit using the method for monitoring the shift in the buried layer. The method for monitoring the shift in the buried layer, among other steps, includes forming a buried layer test structure (200) in, on or over a substrate (210) of a semiconductor device, the buried layer test structure (200) including a first test buried layer (230a) located in or on the substrate (210), the first test buried layer (230a) shifted a predetermined distance with respect to a first test feature (240a). The buried layer test structure (200) further includes a second test buried layer (230b) located in the substrate (210), the second test buried layer (23b) shifted a predetermined but different distance with respect to a second test feature (240b).Type: ApplicationFiled: February 2, 2005Publication date: February 23, 2006Applicant: Texas Instruments, Inc.Inventors: Xinfen Chen, Xiaoju Wu, John Arch, Qingfeng Wang
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Patent number: 5780362Abstract: The present invention relates to a method for forming cobalt disilicide structure on a silicon substrate comprising the steps of depositing a cobalt layer on the substrate, thereafter depositing a refractory metal on the cobalt layer, thereby forming a bilayer structure on the said substrate, and heating the bilayer structure. The present invention also relates to a method for forming self-aligned cobalt disilicide on a metal oxide semiconductor transistor with a source drain and gate regions in a silicon substrate comprising the steps of: depositing a cobalt layer on the substrate, thereafter depositing a refractory metal layer on the cobalt layer, heating the silicon substrate, thereby forming a cobalt dislicide layer on the gate, source, and drain regions of the MOS transistor, and selectively etching the remaining nonsilicide cobalt and refractory metal from the substrate except from the source, drain, and gate regions.Type: GrantFiled: June 4, 1996Date of Patent: July 14, 1998Inventors: Qingfeng Wang, Karen Irma Josef Maex
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Patent number: D844551Type: GrantFiled: November 27, 2017Date of Patent: April 2, 2019Assignee: Beijing Hanergy Solar Power Investment Co., Ltd.Inventors: Jing Wang, Feiyan Si, Qingfeng Wang