Abstract: Provided are a display panel and a display device. The display panel includes data lines, signal wirings and connection wires. The data lines are located in a display region, and the data line includes a first data line and a second data line. The signal wiring includes a first signal wiring and a second signal wiring. The connection wires are located in the display region, the connection wire includes a first connection wire and a second connection wire, where the first connection wire is connected to the first data line and the first signal wiring, and the second connection wire is connected to the second data line and the second signal wiring; the first connection wire includes a first sub-subsection and a first sub-wire which are connected to each other, the second connection wire includes a second sub-subsection and a second sub-wire which are connected to each other.

Abstract: Display panel and display device are provided. The display panel includes a driving circuit includes N-level shift registers connected in cascade with N?2. A shift register of the N-level shift registers includes a first control part and a second control part. The first control part is electrically connected to the second control part. The first control part is configured to control a first output signal, and the first output signal of an i-th level shift register serves as an input signal of a j-th level shift register, where 1?i?N, and 1?j?N. The second control part includes a control unit and a first voltage stabilizing unit.

Abstract: The present disclosure provides a display panel and a display apparatus. The display panel includes a driver circuit including shift registers. The shift register includes a shift control module, configured to receive an input signal, a first clock signal and a second clock signal, and control signals of a first node and a second node; a shift output module, configured to receive the signal of the first node, the signal of the second node, a first level signal and a second level signal, and control an output shift signal; an output control module, configured to receive an output control signal and the shift signal, and control a signal of a third node; a transmission control module, configured to receive the signal of the second node and a signal of the third node, and control a signal of the fourth node; a potential maintaining module; and a drive output module.

Abstract: Display panel and display device are provided. The display panel includes driving circuit including a cascaded N-stage shift register. A stage of the cascaded N-stage shift register includes: shift control module, configured to at least receive an input signal and control signals of a first node and a second node; shift output module, configured to at least receive the signals of the first node and the second node, and control a shift signal; selection control module, configured to at least receive the shift signal and a selection control signal, and control a time for transmitting the selection control signal to the third node; output control module, configured to at least receive the shift signal and a signal of a third node, and control a signal of a fourth node; and signal output module, configured to at least receive the signal of the fourth node, and control a gate driving signal.

Abstract: Display panel and display device are provided. The display panel includes a plurality of shift registers in cascade, for generating primary scan signals, primary scan signals output by adjacent shift registers overlapping; a plurality of gating circuits, electrically connected to the plurality of shift registers in a one-to-one correspondence, for generating scan signals, a frequency of a scan signal of the scan signals being less than or equal to a frequency of a primary scan signal of the primary scan signals; control signal lines, including a first control signal line; and a plurality of shift register areas, each of the plurality of shift register areas comprising at least one shift register.

Abstract: A display panel includes a driving circuit including a first refresh driving line and N stages of first shift register modules. A first shift register module includes a first shift output unit, a refresh driving unit and a refresh control unit. First signal end of the refresh driving unit is connected to the first refresh driving line, second signal end of the refresh driving unit is connected to a trigger signal end, and output end of the refresh driving unit is connected to first end of the refresh control unit, second end of the refresh control unit is connected to output end of the first shift output unit, output end of the refresh control unit is connected to a row of sub-pixels, and the refresh driving unit is configured to provide a pulse control signal to control a valid pulse output duration of the refresh control unit.

Abstract: Provided are a display panel and a display device which belong to the field of display technology. The display panel includes a driver circuit including a shift register, where the shift register includes an input circuit connected to at least an input signal terminal, a first clock signal line, and a first node; a control circuit connected to at least a first voltage signal line, a second voltage signal line, the first node, a second node, and a third node, where the first node and the third node are directly connected or connected through a first adjustment circuit; and an output circuit including a first output circuit and a second output circuit, where the first output circuit is connected to at least the first voltage signal line, the third node, and an output signal terminal.

Abstract: The present disclosure provides a display panel and a display device. A display area of the display panel includes a plurality of pixel circuits arranged in an array. In a same pixel circuit, a bias adjustment module provides a bias adjustment signal to a first electrode of a driving transistor in a bias adjustment phase. The display mode of the display panel includes a first mode. In the first mode, at least some of the pixel circuits are first pixel circuits. A driving cycle of a first pixel circuit includes a data writing frame and a holding frame. The bias adjustment module of the first pixel circuit provides a first bias adjustment signal in the data writing frame, and a second bias adjustment signal in the holding frame, where a voltage of the first bias adjustment signal is different from a voltage of the second bias adjustment signal.

Abstract: A display panel and a display device are provided. A compensation module of a pixel circuit of a display panel is on in a bias adjustment stage, a data write stage, and a time period between the bias adjustment stage and the data write stage; and/or, a reset module of the pixel circuit is on in the bias adjustment stage and a reset stage and is turned off at least after the compensation module is turned on.

Abstract: A display panel includes a driver circuit including shift registers with N stages and being cascade with each other, where N?2, and each shift register includes a first control portion and a second control portion. The first control portion is configured to control a first output signal, where the first output signal of an i-th stage of shift register is an input signal of a j-th stage of shift register, and 1?i?N, 1?j?N. The second control portion includes a first control unit configured to at least receive the first output signal and the frequency control signal, and control a signal of a first node and a second control unit configured to at least receive the signal of the first node and control the second output signal.

Abstract: Provided is a display panel. The display panel includes a pixel circuit and a driver circuit. The pixel circuit includes a drive module and a preset module. The preset module is configured to provide a preset signal for the drive module. The driver circuit is configured to provide a control signal for the preset module. At least part of the time period during which the display panel operates includes a transition phase. The transition phase is between the end of a retention frame of the first data refresh area and the start of a data write frame of the second data refresh area. Alternatively, the transition phase is between the end of a data write frame of the second data refresh area and the start of a retention frame of the first data refresh area.

Abstract: Display panel and display device are provided. The display panel includes a pixel circuit and a light-emitting element. The pixel circuit includes a driving transistor and an initialization transistor. The initialization transistor is configured to provide an initialization signal for a preset node. The preset node is a gate of the driving transistor, or an anode of the light-emitting element. The pixel circuit includes an oxide semiconductor transistor and a silicon transistor. An active layer of the oxide semiconductor transistor includes an oxide semiconductor, and an active layer of the silicon transistor includes silicon. The pixel circuit includes a first pixel circuit and a second pixel circuit. The first pixel circuit includes a first initialization transistor. The second pixel circuit includes a second initialization transistor. An active layer of the first initialization transistor is connected to an active layer of the second initialization transistor through a first connection wire.

Abstract: Display panel and display device are provided. The display panel includes a pixel circuit and a light-emitting element. The pixel circuit includes a driving transistor and an initialization transistor. The initialization transistor is configured to provide an initialization signal for a preset node. The preset node is a gate of the driving transistor, or an anode of the light-emitting element. The pixel circuit includes an oxide semiconductor transistor and a silicon transistor. An active layer of the oxide semiconductor transistor includes an oxide semiconductor, and an active layer of the silicon transistor includes silicon. The pixel circuit includes a first pixel circuit and a second pixel circuit. The first pixel circuit includes a first initialization transistor. The second pixel circuit includes a second initialization transistor. An active layer of the first initialization transistor is connected to an active layer of the second initialization transistor through a first connection wire.

Abstract: Display panel and display device are provided. The display panel includes a pixel circuit and a light-emitting element. The pixel circuit includes a driving transistor and an initialization transistor. The initialization transistor is configured to provide an initialization signal for a preset node. The preset node is a gate of the driving transistor, or an anode of the light-emitting element. The pixel circuit includes an oxide semiconductor transistor and a silicon transistor. An active layer of the oxide semiconductor transistor includes an oxide semiconductor, and an active layer of the silicon transistor includes silicon. The pixel circuit includes a first pixel circuit and a second pixel circuit. The first pixel circuit includes a first initialization transistor. The second pixel circuit includes a second initialization transistor. An active layer of the first initialization transistor is connected to an active layer of the second initialization transistor through a first connection wire.

Abstract: A display panel includes a driver circuit including shift registers with N stages and being cascade with each other, where N?2, and each shift register includes a first control portion and a second control portion. The first control portion is configured to control a first output signal, where the first output signal of an i-th stage of shift register is an input signal of a j-th stage of shift register, and 1?i?N, 1?j?N. The second control portion is configured to receive at least the first output signal and a frequency control signal and control a second output signal. In a case where the first output signal is an effective pulse and a time period of the effective pulse is within a time period of an effective pulse of the frequency control signal, the second output signal is the effective pulse.

Abstract: A display panel includes a base substrate, a first transistor and a second transistor. The first transistor and the second transistor are formed on the base substrate. The first transistor includes a first active layer, a first gate electrode, a first source electrode, and a first drain electrode. The first active layer includes silicon. The second transistor includes a second active layer, a second gate electrode, a second source electrode, and a second drain electrode. The second active layer includes an oxide semiconductor. A length of a channel region of the first transistor is L1. Along a direction perpendicular to the base substrate, a distance between the first gate electrode and the first active layer is D1. The first transistor further includes a third gate electrode. Along the direction perpendicular to the base substrate, a distance between the third gate electrode and the first active layer is D3, and D1<D3.

Abstract: Display panel and display device are provided. The display panel includes a pixel circuit and a light-emitting element. The pixel circuit includes a driving transistor and an initialization transistor. The initialization transistor is configured to provide an initialization signal for a preset node. The preset node is a gate of the driving transistor, or an anode of the light-emitting element. The pixel circuit includes an oxide semiconductor transistor and a silicon transistor. An active layer of the oxide semiconductor transistor includes an oxide semiconductor, and an active layer of the silicon transistor includes silicon. The pixel circuit includes a first pixel circuit and a second pixel circuit. The first pixel circuit includes a first initialization transistor. The second pixel circuit includes a second initialization transistor. An active layer of the first initialization transistor is connected to an active layer of the second initialization transistor through a first connection wire.

Abstract: A display panel includes a base substrate, a third transistor and a fourth transistor. The third transistor and the fourth transistor are formed on the base substrate. The third transistor includes a sixth gate electrode, a third active layer, a third source electrode, and a third drain electrode. The third active layer includes an oxide semiconductor. The fourth transistor includes an eighth gate electrode, a fourth active layer, a fourth source electrode, and a fourth drain electrode. The fourth active layer includes another oxide semiconductor. Along a direction perpendicular to the base substrate, a distance between the sixth gate electrode and the third active layer is D6. A channel region of the third transistor defined by the sixth gate electrode is a sixth channel region. A length of the sixth channel region is L6. A sixth area S6=L6×D6.

Abstract: Disclosed are a display panel and a display device. The display panel includes a pixel circuit and a light-emitting element, in the pixel circuit, the drive device includes a drive transistor; the reset device includes a first double-gate transistor, and a connection node between the first sub-transistor and the second sub-transistor is a second node. The pixel circuit is connected to a first power supply voltage signal terminal, and is configured to receive a first power supply voltage signal, and the first power supply voltage signal is a constant high level signal; and the pixel circuit includes a first capacitor, a first pole plate of the first capacitor is connected to the first power supply voltage signal terminal, and a second pole plate of the first capacitor is connected to the second node.

Abstract: Provided are a display panel, a driving method thereof and a display device. The display panel includes: a pixel circuit and a light-emitting element, where the pixel circuit includes a light emitting control module, a drive module and a compensation module; the light emitting control module includes a first light emitting control module configured to selectively provide a first power supply signal for the drive module; the drive module is configured to provide a drive current for the light-emitting element and comprises a drive transistor; the compensation module is configured to compensate a threshold voltage of the drive transistor; and a working process of the pixel circuit includes a light emitting stage and a bias stage.