Abstract: A shift register circuit and its driving method, a display panel, and a display device are provided. The shift register circuit includes an input module, a first inverter, a second inverter, and an output module. The input module is connected to a first input terminal, a second input terminal, a third input terminal, and a first electrical-level terminal, to respond to signals from the second and third input terminal and control a voltage of a first node. In the first inverter, an input terminal is connected to the first node, and an output terminal is connected to a second node. In the second inverter, an input terminal is connected to the second node, and an output terminal is connected to the first node. The output module provides a signal of the fourth input terminal to an output terminal of the output module, and also provides a voltage of a first power terminal to the output terminal of the output module.

Abstract: Provided are a display panel and a display device. The display panel includes a driving circuit comprising N stages of cascaded shift registers. Each shift register includes a first control unit, a second control unit, a third control unit, and a fourth control unit. The first control unit is configured to receive an input signal and control a signal of a first node. The second control unit is configured to receive a first voltage signal and control a signal of a second node. The third control unit is configured to receive a signal of a fourth node and control an output signal, or receive a second voltage signal and control the output signal. The fourth control unit is configured to receive the first voltage signal and a third voltage signal and control the signal of the fourth node.

Abstract: An inverter, a method for driving an inverter, a driving circuit and a display panel are provided. An inverter includes a first module; a second module; an initial signal input terminal; and a first level signal input terminal. The first module includes a first transistor, a second transistor, and a third transistor; control terminals of the first transistor and the second transistor are both electrically connected to the initial signal input terminal; a first terminal of the third transistor is electrically connected to the first level signal input terminal; a first terminal of the second transistor is electrically connected to a first terminal of the second transistor; a second terminal of the second transistor is electrically connected to a control terminal of the third transistor; the first module includes a leakage current control component at least electrically connected with the second terminal of the first transistor.

Abstract: A display panel and a display device are provided. The display panel includes a driving circuit. The driving circuit includes N levels of shift registers cascaded with each other, where N 2. A shift register of the N levels of shift registers includes: a first control unit, configured to receive an input signal and control a signal of a first node in response to a first clock signal; a second control unit, configured to receive a first voltage signal and a second voltage signal, and control a signal of a second node in response to the signal of the first node, the first clock signal, and a second clock signal; and a third control unit, configured to receive the first voltage signal and the second voltage signal, and control an output signal in response to the signal of the second node and a signal of the third node.

Abstract: A display panel and a display device are provided. The display panel includes a driving circuit including N-level shift registers cascaded with each other, where N is greater than or equal to two. A shift register includes a first control unit configured to receive an input signal, and control a signal of a first node; a second control unit configured to receive a first voltage signal and a second voltage signal, and control a signal of a second node; a third control unit configured to receive the first voltage signal and the second voltage signal, and control a signal of a fourth node; and a fourth control unit configured to receive a third voltage signal and a fourth voltage signal, and generate an output signal. The first and third voltage signals are high-level signals, and the second and fourth voltage signals are low-level signals.

Abstract: A shift register circuit and its driving method, a display panel, and a display device are provided. The shift register circuit includes an input module, a first inverter, a second inverter, and an output module. The input module is connected to a first input terminal, a second input terminal, a third input terminal, and a first electrical-level terminal, to respond to signals from the second and third input terminal and control a voltage of a first node. In the first inverter, an input terminal is connected to the first node, and an output terminal is connected to a second node. In the second inverter, an input terminal is connected to the second node, and an output terminal is connected to the first node. The output module provides a signal of the fourth input terminal to an output terminal of the output module, and also provides a voltage of a first power terminal to the output terminal of the output module.

Abstract: A display panel and a display device are provided. The display panel includes a driving circuit including N-level shift registers cascaded with each other, where N is greater than or equal to two. A shift register includes a first control unit configured to receive an input signal, and control a signal of a first node; a second control unit configured to receive a first voltage signal and a second voltage signal, and control a signal of a second node; a third control unit configured to receive the first voltage signal and the second voltage signal, and control a signal of a fourth node; and a fourth control unit configured to receive a third voltage signal and a fourth voltage signal, and generate an output signal. The first and third voltage signals are high-level signals, and the second and fourth voltage signals are low-level signals.

Abstract: A display panel and a display device are provided. A shift register of the display panel includes a first control unit, configured to receive an input signal and control a signal of a first node in response to a first clock signal; a second control unit, configured to receive a first voltage signal and control a signal of a second node in response to the input signal and the first clock signal; a third control unit, configured to receive the first voltage signal and a second voltage signal and control a signal of a fourth node in response to the signal of the second node and a signal of a third node; and a fourth control unit, configured to receive a third voltage signal and a fourth voltage signal and generate an output signal in response to the signals of the second node and the fourth node.

Abstract: The present disclosure provides a shift register and a driving method thereof, a scan driving circuit, a display panel, and a display device. The shift register includes an input module; a control module; a reset module; a first output module; a second output module; and a stabilization module, that a phase of a signal output from the second output module lags behind a phase of a signal output from the first output module, and does not overlap with the phase of the signal output from the first output module.

Abstract: The present disclosure provides a shift register and a driving method thereof, a scan driving circuit, a display panel, and a display device. The shift register includes an input module; a control module; a reset module; a first output module; a second output module; and a stabilization module, that a phase of a signal output from the second output module lags behind a phase of a signal output from the first output module, and does not overlap with the phase of the signal output from the first output module.

Abstract: A display panel and a display device are provided. The display panel includes a driving circuit. The driving circuit includes N-level shift registers cascaded with each other, where N is greater than or equal to two. A shift register includes: a first control unit configured to receive an input signal and control a signal of a first node; a second control unit configured to receive a first voltage signal and control a signal of a second node; a third control unit configured to receive the first voltage signal and generate an output signal, or receive a second voltage signal and generate an output signal in response to a signal of a third node connected to the first node; and a fourth control unit configured to receive the second voltage signal and control the signal of the first node. The first and second voltage signals are high-level and low-level signals, respectively.

Abstract: A display panel and a display device are provided. The display panel includes at least one driving circuit and at least one pixel circuit. A driving circuit provides a driving signal for a pixel circuit. The driving circuit includes N-level shift registers cascaded with each other, where N is greater than or equal to two. A shift register includes at least one first active layer, and an active layer with a largest area is a first preset active layer. The pixel circuit includes at least one second active layer, where an active layer with a largest area among active layers containing silicon is a second preset active layer, and an active layer with a largest area among active layers containing oxide semiconductor is a third preset active layer. The first preset active layer has an area greater than the second preset active layer and the third preset active layer.

Abstract: A display panel and a display device are provided in the present disclosure. The display panel includes a base substrate, a first transistor, a second transistor, a pixel circuit, and a drive circuit. A first active layer of the first transistor includes silicon; and a second active layer of the second transistor includes an oxide semiconductor. A length of a channel region of the first transistor is LL a distance between a first gate electrode and the first active layer is D1, and a first area S1=L1×D1; and a length of a channel region of the second transistor is L2, a distance between a second gate electrode and the second active layer is D2, and a second area S2=L2×D2, where S1<S2. The second transistor is included in the drive circuit, and the first transistor is included in one of the pixel circuit and the drive circuit.

Abstract: Provided are a pixel driving circuit, a driving method, a display panel and a display device. The pixel driving circuit includes: a data writing device, a voltage stabilizing storage device, a driving device and a light-emitting component; where the data writing device is configured for transmitting a data signal voltage; the driving device is configured for generating a driving current according to the data signal voltage transmitted by the data writing device; the voltage stabilizing storage device is configured for storing the data signal voltage transmitted to the driving device; the light-emitting component is configured for emitting light in response to the driving current generated by the driving device; where the voltage stabilizing storage device includes at least two voltage stabilizing storage sub-devices connected in parallel, each voltage stabilizing storage sub-device includes a capacitor, at least one of the voltage stabilizing storage sub-devices includes a switch device.

Abstract: Provided are a display panel and a display device. The display panel includes a driving circuit. The driving circuit includes N stages of cascaded shift registers. Each shift register includes a first control unit, a second control unit, and a third control unit. The first control unit is configured to receive a third voltage signal and control a signal of a fourth node in response to a frequency control signal. The second control unit is configured to receive a fourth voltage signal and control a signal of a fifth node in response to the frequency control signal. The third control unit is configured to receive a fifth voltage signal and generate an output signal in response to a signal of the fourth node; or the third control unit is configured to receive a sixth voltage signal and generate an output signal in response to a signal of the fifth node.

Abstract: Provided are a display panel and a display device. The display panel includes a driving circuit comprising N stages of cascaded shift registers. Each shift register includes a first control unit, a second control unit, a third control unit, and a fourth control unit. The first control unit is configured to receive an input signal and control a signal of a first node. The second control unit is configured to receive a first voltage signal and control a signal of a second node. The third control unit is configured to receive a signal of a fourth node and control an output signal, or receive a second voltage signal and control the output signal. The fourth control unit is configured to receive the first voltage signal and a third voltage signal and control the signal of the fourth node.

Abstract: Provided are a display panel and a display device. The display panel includes a driver circuit including N stages of cascaded shift registers, where N?2. Each shift register includes a first control part and a second control part. The second control part includes a first control unit and a second control unit. The first control unit is configured to receive a signal of a preset node and a first output control signal and control a signal of a fourth node, where the preset node is one of a second node or a third node. A first output control signal received by a shift register at an M1-th stage is a signal of the preset node of a shift register at an M2-th stage, where 1?M1?N, 1?M2?N, 1?|M1?M2|?i, and 2?i?N?1.

Abstract: Disclosed are a display panel and a display device. The display panel includes a pixel circuit and a light-emitting element, in the pixel circuit, the driving module includes a drive transistor, and a gate of the drive transistor is connected to a first node; a reset module includes a first sub-transistor and a second sub-transistor, and a connection node between the first sub-transistor and the second sub-transistor is a second node; a compensation module includes a third sub-transistor and a fourth sub-transistor, a connection node between the third sub-transistor and the fourth sub-transistor is a third node; in a first stage, a first double-gate transistor and a second double-gate transistor are both turned off, and the first node, the second node, and the third node satisfy: (V2?V1)×(V1?V3)>0.

Abstract: Provided are a display panel, a driving method thereof and a display device. The display panel includes: a pixel circuit and a light-emitting element, where the pixel circuit includes a light emitting control module, a drive module and a compensation module; the light emitting control module includes a first light emitting control module configured to selectively provide a first power supply signal for the drive module; the drive module is configured to provide a drive current for the light-emitting element and comprises a drive transistor; the compensation module is configured to compensate a threshold voltage of the drive transistor; and a working process of the pixel circuit includes a light emitting stage and a bias stage.

Abstract: A display panel and a display device are provided. The display panel includes sub-pixels located in a display area, first and second substrate that are oppositely arranged, a first electrode layer, an antenna layer, and a magnet isolating layer including at least one magnet isolator. The first electrode layer is located at a side of the first substrate facing the second substrate, and a first electrode of the first electrode layer covers at least two sub-pixels in a first direction. The antenna layer includes at least one antenna including a multi-turn antenna coil. One magnet isolator corresponds to at least one antenna. Along a thickness direction of the display panel, the magnet isolating layer is disposed between the first electrode layer and the antenna layer. The magnet isolator is disposed between the first electrode and the antenna coil.