Patents by Inventor Qingqing Liang
Qingqing Liang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20240154406Abstract: A radio frequency (RF) device is described. The RF device includes a first RF switch coupled in series to a first RF port and coupled in parallel to an RF common (RFC) port. The RF device also includes an electrostatic discharge (ESD) dissipation switch coupled to the RF common port. The ESD dissipation switch includes a switch field effect transistor (FET). The switch FET includes a gate on an active layer of a substrate, and a symmetric silicide area block (SAB) on a first sidewall spacer and a second sidewall spacer, opposite the first sidewall spacer, and on a gate surface of the gate, opposite the active layer of the substrate.Type: ApplicationFiled: November 8, 2022Publication date: May 9, 2024Inventors: George Pete IMTHURN, Woojin CHOI, Maurice Adrianus DE JONGH, Jeffrey Donald MILLER, Qingqing LIANG
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Publication number: 20240105797Abstract: Disclosed are apparatuses including transistor and methods for fabricating the same. The transistor may include a drain substantially enclosed in a drain silicide layer, wherein an integral drain via portion of the drain silicide layer is coupled to a second drain contact and wherein a first drain via couples the drain silicide layer to a first drain contact. The transistor may include a source substantially enclosed in a source silicide layer, wherein an integral source via portion of the source silicide layer is coupled to a second source contact and wherein a first source via couples the source silicide layer to a first source contact. The transistor may include a gate disposed between the source and the drain.Type: ApplicationFiled: September 22, 2022Publication date: March 28, 2024Inventors: Qingqing LIANG, Haining YANG, Jonghae KIM, Periannan CHIDAMBARAM, George Pete IMTHURN
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Publication number: 20240105728Abstract: Disclosed are standard cells, transistors, and methods for fabricating the same. In an aspect, a transistor includes a drain and a source each including a first drain/source silicide layer on a frontside surface of the drain/source and a second drain/source silicide layer on a backside surface of the drain/source. The first drain silicide layer is coupled to a first drain contact structure or the second drain silicide layer is coupled to a second drain contact structure. The first source silicide layer is coupled to a first source contact structure or the second source silicide layer is coupled to a second source contact structure. A gate structure is disposed between the source and the drain. A channel is at least partially enclosed by the gate structure and disposed between the source and the drain and is recessed from the backside surfaces of the source and drain.Type: ApplicationFiled: September 21, 2023Publication date: March 28, 2024Inventors: Qingqing LIANG, Haining YANG, Jonghae KIM, Periannan CHIDAMBARAM, George Pete IMTHURN, Jun YUAN, Giridhar NALLAPATI, Deepak SHARMA
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Publication number: 20240096750Abstract: Disclosed are integrated circuit structures with through-substrate vias (TSVs) processed through self-aligned contact modules. As a result, much smaller and/or denser TSVs are formed with low mechanical stress. The denser TSVs allow for more flexible wiring options.Type: ApplicationFiled: September 19, 2022Publication date: March 21, 2024Inventors: Qingqing LIANG, Periannan CHIDAMBARAM, George Pete IMTHURN, Stanley Seungchul SONG
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Publication number: 20230282716Abstract: Disclosed is a transistor of a device that has double side contacts in which at least a drain contact is on the opposite side of the gate. In this way, gate resistance can be reduced without increasing parasitic capacitances between gate and drain.Type: ApplicationFiled: March 4, 2022Publication date: September 7, 2023Inventors: Qingqing LIANG, George Pete IMTHURN, Yun Han CHU, Sivakumar KUMARASAMY
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Publication number: 20210242322Abstract: Certain aspects of the present disclosure generally relate to a semiconductor device having a backside gate contact. An example semiconductor device generally includes a transistor disposed above a substrate, wherein the transistor comprises a gate region, a channel region, a source region, and a drain region and wherein the gate region is disposed adjacent to the channel region. The semiconductor device further includes a backside gate contact that is electrically coupled to a bottom surface of the gate region and that extends below a bottom surface of the substrate.Type: ApplicationFiled: January 31, 2020Publication date: August 5, 2021Inventors: Qingqing LIANG, Sivakumar KUMARASAMY, George Pete IMTHURN, Sinan GOKTEPELI
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Patent number: 11081559Abstract: Certain aspects of the present disclosure generally relate to a semiconductor device having a backside gate contact. An example semiconductor device generally includes a transistor disposed above a substrate, wherein the transistor comprises a gate region, a channel region, a source region, and a drain region and wherein the gate region is disposed adjacent to the channel region. The semiconductor device further includes a backside gate contact that is electrically coupled to a bottom surface of the gate region and that extends below a bottom surface of the substrate.Type: GrantFiled: January 31, 2020Date of Patent: August 3, 2021Assignee: QUALCOMM IncorporatedInventors: Qingqing Liang, Sivakumar Kumarasamy, George Pete Imthurn, Sinan Goktepeli
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Patent number: 11081582Abstract: A method of constructing an integrated circuit (IC) includes fabricating a metal oxide semiconductor field effect transistor (MOSFET) on a first surface of an insulator layer of the integrated circuit. The insulator layer is supported by a sacrificial substrate. The MOSFET includes an extended drain region. The method deposits a front-side dielectric layer on the MOSFET, bonds a handle substrate to the front-side dielectric layer, and then removes the sacrificial substrate. The method also fabricates multiple back gates on a second surface of the insulator layer. The second surface is opposite the first surface.Type: GrantFiled: February 11, 2020Date of Patent: August 3, 2021Assignee: QUALCOMM IncorporatedInventors: Qingqing Liang, Ravi Pramod Kumar Vedula, Sivakumar Kumarasamy, George Pete Imthurn, Sinan Goktepeli
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Patent number: 10896958Abstract: In certain aspects, an apparatus comprises an SOI MOSFET having a diffusion region as a source or a drain on a back insulating layer, wherein the diffusion region has a front diffusion side and a back diffusion side opposite to the front diffusion side; a silicide layer on the front diffusion side having a back silicide side facing the diffusion region and a front silicide side opposite to the back silicide side; and a backside contact connected to the silicide layer, wherein at least a portion of the backside contact is in the back insulating layer.Type: GrantFiled: November 21, 2019Date of Patent: January 19, 2021Assignee: QUALCOMM IncorporatedInventors: Sinan Goktepeli, George Pete Imthurn, Yun Han Chu, Qingqing Liang
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Publication number: 20200373315Abstract: Certain aspects of the present disclosure are generally directed to non-volatile memory (NVM) and techniques for operating and fabricating NVM. Certain aspects provide a memory cell for implementing NVM. The memory cell generally includes a first semiconductor region, a second semiconductor region, and a third semiconductor region, the second semiconductor region being disposed between and having a different doping type than the first and third semiconductor regions. The memory cell also includes a fourth semiconductor region disposed adjacent to and having the same doping type as the third semiconductor region, a first front gate region disposed adjacent to the second semiconductor region, and a first floating front gate region disposed adjacent to the third semiconductor region. In certain aspects, the memory cell includes a back gate region, wherein the second semiconductor region is between the first front gate region and at least a portion of the back gate region.Type: ApplicationFiled: May 22, 2019Publication date: November 26, 2020Inventors: Qingqing LIANG, George Pete IMTHURN, Sinan GOKTEPELI, Sivakumar KUMARASAMY
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Publication number: 20200365740Abstract: Certain aspects of the present disclosure are directed to a memory cell implemented using front and back gate regions. One example memory cell generally includes a first semiconductor region, a second semiconductor region, and a third semiconductor region, the second semiconductor region being disposed between the first semiconductor region and the third semiconductor region. The memory cell may also include a front gate region disposed above the second semiconductor region, a floating back gate region, a first portion of the floating back gate region being disposed below the second semiconductor region, and a non-insulative region disposed adjacent to the floating back gate region.Type: ApplicationFiled: May 17, 2019Publication date: November 19, 2020Inventors: Qingqing LIANG, Peter Graeme CLARKE, George Pete IMTHURN, Sinan GOKTEPELI, Sivakumar KUMARASAMY
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Patent number: 10840387Abstract: Certain aspects of the present disclosure provide semiconductor variable capacitors. One example semiconductor variable capacitor generally includes a semiconductor region, a first insulator region disposed below the semiconductor region, a first non-insulative region disposed below the first insulator region, a second non-insulative region disposed adjacent to the semiconductor region, and a third non-insulative region disposed adjacent to the semiconductor region, wherein the semiconductor region is disposed between the second non-insulative region and the third non-insulative region. In certain aspects, the semiconductor variable capacitor may include a second insulator region disposed above the semiconductor region and a second semiconductor region disposed above the second insulator region.Type: GrantFiled: April 5, 2018Date of Patent: November 17, 2020Assignee: QUALCOMM IncorporatedInventors: Fabio Alessio Marino, Sinan Goktepeli, Narasimhulu Kanike, Qingqing Liang, Paolo Menegoli, Francesco Carobolante, Aristotele Hadjichristos
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Patent number: 10840383Abstract: Certain aspects of the present disclosure are directed to a memory cell implemented using front and back gate regions. One example memory cell generally includes a first semiconductor region, a second semiconductor region, and a third semiconductor region, the second semiconductor region being disposed between the first semiconductor region and the third semiconductor region. The memory cell may also include a front gate region disposed above the second semiconductor region, a floating back gate region, a first portion of the floating back gate region being disposed below the second semiconductor region, and a non-insulative region disposed adjacent to the floating back gate region.Type: GrantFiled: May 17, 2019Date of Patent: November 17, 2020Assignee: Qualcomm IncorporatedInventors: Qingqing Liang, Peter Graeme Clarke, George Pete Imthurn, Sinan Goktepeli, Sivakumar Kumarasamy
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Patent number: 10748934Abstract: An integrated circuit device includes a portion of a support wafer (e.g., a handle wafer), silicon on insulator layer, a first active device, and a second active device. The first active device has a first semiconductor thickness in a dielectric layer (e.g., a buried oxide layer). The first active device is on the SOI layer. The second active device has a second semiconductor thickness in the same dielectric layer as the first active device. The supporting wafer supports the first active device and the second active device. The second active device is also on the SOI layer. The first and second thicknesses are different from one another.Type: GrantFiled: August 28, 2018Date of Patent: August 18, 2020Assignee: QUALCOMM IncorporatedInventors: Qingqing Liang, Stephen Alan Fanelli, Sinan Goktepeli
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Patent number: 10707866Abstract: A dual sided contact switch has a first independent drain/source region of a multi-gate active device. The dual sided contact switch also has a first shared drain/source region of the multi-gate active device. The dual sided contact switch has a second independent drain/source region of the multi-gate active device, adjacent to the first shared drain/source region. The dual sided contact switch also has a second shared drain/source region of the multi-gate active device, adjacent to the first independent drain/source region. The dual sided contact switch has a gate region between the first independent drain/source region and the first shared drain/source region, and also between the second independent drain/source region and the second shared drain/source region.Type: GrantFiled: December 21, 2018Date of Patent: July 7, 2020Assignee: QUALCOMM IncorporatedInventors: Qingqing Liang, Ravi Pramod Kumar Vedula, George Peter Imthurn, Christopher Nelles Brindle, Sinan Goktepeli
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Publication number: 20200204175Abstract: A dual sided contact switch has a first independent drain/source region of a multi-gate active device. The dual sided contact switch also has a first shared drain/source region of the multi-gate active device. The dual sided contact switch has a second independent drain/source region of the multi-gate active device, adjacent to the first shared drain/source region. The dual sided contact switch also has a second shared drain/source region of the multi-gate active device, adjacent to the first independent drain/source region. The dual sided contact switch has a gate region between the first independent drain/source region and the first shared drain/source region, and also between the second independent drain/source region and the second shared drain/source region.Type: ApplicationFiled: December 21, 2018Publication date: June 25, 2020Inventors: Qingqing LIANG, Ravi Pramod Kumar VEDULA, George Pete IMTHURN, Christopher Nelles BRINDLE, Sinan GOKTEPELI
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Publication number: 20200185522Abstract: A method of constructing an integrated circuit (IC) includes fabricating a metal oxide semiconductor field effect transistor (MOSFET) on a first surface of an insulator layer of the integrated circuit. The insulator layer is supported by a sacrificial substrate. The MOSFET includes an extended drain region. The method deposits a front-side dielectric layer on the MOSFET, bonds a handle substrate to the front-side dielectric layer, and then removes the sacrificial substrate. The method also fabricates multiple back gates on a second surface of the insulator layer. The second surface is opposite the first surface.Type: ApplicationFiled: February 11, 2020Publication date: June 11, 2020Inventors: Qingqing LIANG, Ravi Pramod Kumar VEDULA, Sivakumar KUMARASAMY, George Pete IMTHURN, Sinan GOKTEPELI
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Patent number: 10622492Abstract: Certain aspects of the present disclosure provide semiconductor variable capacitors. One example semiconductor variable capacitor generally includes a semiconductor region, an insulative layer, and a first non-insulative region, the insulative layer being disposed between the semiconductor region and the first non-insulative region. In certain aspects, the semiconductor variable capacitor may also include a second non-insulative region disposed adjacent to the semiconductor region, and a third non-insulative region disposed adjacent to the semiconductor region, the second non-insulative region and the third non-insulative region having different doping types. In certain aspects, the semiconductor variable capacitor may also include an implant region disposed between the semiconductor region and the insulative layer. The implant region may be used to adjust the flat-band voltage of the semiconductor variable capacitor.Type: GrantFiled: January 15, 2018Date of Patent: April 14, 2020Assignee: QUALCOMM IncorporatedInventors: Fabio Alessio Marino, Narasimhulu Kanike, Francesco Carobolante, Paolo Menegoli, Qingqing Liang
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Patent number: 10615294Abstract: A variable capacitor includes a mesa on a substrate. The mesa has multiple III-V semiconductor layers and includes a first side and a second side opposite the first side. The first side has a first sloped portion and a first horizontal portion. The second side has a second sloped portion and a second horizontal portion. A control terminal is on a third side of the mesa. A first terminal is on the first side of the mesa. The first terminal is disposed on the first horizontal portion and the first sloped portion. A second terminal is also on the substrate.Type: GrantFiled: June 13, 2018Date of Patent: April 7, 2020Assignee: QUALCOMM IncorporatedInventors: Gengming Tao, Xia Li, Bin Yang, Qingqing Liang, Francesco Carobolante
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Patent number: 10608124Abstract: Certain aspects of the present disclosure provide a semiconductor device. One example semiconductor device generally includes a semiconductor region, an insulative layer, a first terminal, and a first non-insulative region coupled to the first terminal, the insulative layer being disposed between the first non-insulative region and the semiconductor region. In certain aspects, the insulative layer is disposed adjacent to a first side of the semiconductor region. In certain aspects, the semiconductor device also includes a second terminal, and a first silicide layer coupled to the second terminal and disposed adjacent to a second side of the semiconductor region, the first side and the second side being opposite sides of the semiconductor region.Type: GrantFiled: April 19, 2018Date of Patent: March 31, 2020Assignee: QUALCOMM IncorporatedInventors: Sinan Goktepeli, Fabio Alessio Marino, Narasimhulu Kanike, Plamen Vassilev Kolev, Qingqing Liang, Paolo Menegoli, Francesco Carobolante, Aristotele Hadjichristos