Abstract: A method of determining a number of charged particles incident on a detector within a period may include generating a first signal that is based on a charged particle impacting a sensing element of the detector, performing processing using the first signal based on a predetermined characteristic of a charged particle arrival event on the detector, and outputting a count signal based on the processing.

Abstract: The present disclosure relates to a magnetic field sensor circuit including at least one coil for measuring a magnetic field, a first stage amplifier circuit coupled to the coil and having a first transfer function with a pole at a first frequency, and a second stage amplifier circuit coupled to an output of the first stage amplifier circuit and having a second transfer function with a zero at the first frequency. In some embodiments, a temperature dependent frequency drift of the pole of the first transfer function corresponds to a temperature dependent frequency drift of the zero of the second transfer function.

Abstract: The present disclosure relates to a magnetic field sensor circuit including at least one coil for measuring a magnetic field, a first stage amplifier circuit coupled to the coil and having a first transfer function with a pole at a first frequency, and a second stage amplifier circuit coupled to an output of the first stage amplifier circuit and having a second transfer function with a zero at the first frequency. In some embodiments, a temperature dependent frequency drift of the pole of the first transfer function corresponds to a temperature dependent frequency drift of the zero of the second transfer function.

Abstract: A method of differential signal transfer from a differential input Vinp and Vinn having a common mode input voltage that can be higher than the power supply voltage by providing an input chopper having first through fourth chopper transistors, each having a source, a drain and a gate, the input chopper having Vinp and Vinn as a differential input, providing an output chopper, capacitively coupling a differential output Voutp and Voutn of the input chopper to a differential input of the output chopper, capacitively coupling a clock to the input chopper and coupling the clock to the output chopper, the clock having a first phase and a second phase opposite from the first phase, the first phase being coupled to the gates of the first and second transistors and the second phase being coupled to the gates of the third and fourth transistors, and providing protection of the gates of the first through fourth transistors from excessive voltages. Various embodiments are disclosed.

Abstract: Fast-settling capacitive-coupled amplifiers are disclosed. The amplifiers use two Capacitive Coupled paths embedded in a Multipath Hybrid Nested Miller Compensation topology. One path is a direct high frequency path and the other path is a slower stabilization path. This combination results in a flat frequency response to and through the chopper frequency, and a fast settling response. Various exemplary embodiments are disclosed, including operational amplifier and instrumentation amplifier configurations.

Abstract: A method of differential signal transfer from a differential input Vinp and Vinn having a common mode input voltage that can be higher than the power supply voltage by providing an input chopper having first through fourth chopper transistors, each having a source, a drain and a gate, the input chopper having Vinp and Vinn as a differential input, providing an output chopper, capacitively coupling a differential output Voutp and Voutn of the input chopper to a differential input of the output chopper, capacitively coupling a clock to the input chopper and coupling the clock to the output chopper, the clock having a first phase and a second phase opposite from the first phase, the first phase being coupled to the gates of the first and second transistors and the second phase being coupled to the gates of the third and fourth transistors, and providing protection of the gates of the first through fourth transistors from excessive voltages. Various embodiments are disclosed.

Abstract: A method of differential signal transfer from a differential input Vinp and Vinn having a common mode input voltage that can be higher than the power supply voltage by providing an input chopper having Vinp and Vinn as a differential input, providing an output chopper, capacitively coupling a differential output Voutp and Voutn of the input chopper to a differential input of the output chopper, capacitively coupling a clock to the input chopper and coupling the clock to the output chopper, the clock having a first phase and a second phase opposite from the first phase, the first phase being coupled to the gates of the first and second transistors and the second phase being coupled to the gates of the third and fourth transistors, and providing protection of the gates of the first through fourth transistors from excessive voltages. Various embodiments are disclosed.

Abstract: Fast-settling capacitive-coupled amplifiers are disclosed. The amplifiers use two Capacitive Coupled paths embedded in a Multipath Hybrid Nested Miller Compensation topology. One path is a direct high frequency path and the other path is a slower stabilization path. This combination results in a flat frequency response to and through the chopper frequency, and a fast settling response. Various exemplary embodiments are disclosed, including operational amplifier and instrumentation amplifier configurations.

Abstract: A method of differential signal transfer from a differential input Vinp and Vinn having a common mode input voltage that can be higher than the power supply voltage by providing an input chopper having Vinp and Vinn as a differential input, providing an output chopper, capacitively coupling a differential output Voutp and Voutn of the input chopper to a differential input of the output chopper, capacitively coupling a clock to the input chopper and coupling the clock to the output chopper, the clock having a first phase and a second phase opposite from the first phase, the first phase being coupled to the gates of the first and second transistors and the second phase being coupled to the gates of the third and fourth transistors, and providing protection of the gates of the first through fourth transistors from excessive voltages. Various embodiments are disclosed.